Patents by Inventor Steven Paul Vanderwiel
Steven Paul Vanderwiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9495498Abstract: An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.Type: GrantFiled: September 14, 2012Date of Patent: November 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel, Patrick Ronald Varekamp
-
Patent number: 8736068Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.Type: GrantFiled: March 16, 2012Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel
-
Patent number: 8445918Abstract: A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.Type: GrantFiled: August 13, 2010Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel
-
Publication number: 20130011968Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel
-
Publication number: 20130009324Abstract: An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel, Patrick Ronald Varekamp
-
Patent number: 8330489Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.Type: GrantFiled: April 28, 2009Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel, Patrick Ronald Varekamp
-
Patent number: 8293578Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.Type: GrantFiled: October 26, 2010Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel
-
Publication number: 20120198406Abstract: An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.Type: ApplicationFiled: March 16, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel, Patrick Ronald Varekamp
-
Publication number: 20120187570Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.Type: ApplicationFiled: March 16, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel
-
Publication number: 20120124291Abstract: A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: International Business Machines CorporationInventors: Heather D. Achilles, Timothy Hume Heil, Anil Krishna, Nicholas David Lindberg, Steven Paul VanderWiel, Shaul Yifrach
-
Publication number: 20120098140Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.Type: ApplicationFiled: October 26, 2010Publication date: April 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel
-
Patent number: 7826399Abstract: A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.Type: GrantFiled: March 5, 2008Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Timothy Hume Heil, Michael Steven Siegel, Jeffrey R. Summers, Steven Paul VanderWiel
-
Publication number: 20100271071Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Russell Dean Hoover, Charles Luther Johnson, Steven Paul VanderWiel, Patrick Ronald Varekamp
-
Patent number: 7760669Abstract: In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.Type: GrantFiled: June 27, 2006Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Timothy Hume Heil, Michael Steven Siegel, Jeffrey R. Summers, Steven Paul VanderWiel
-
Publication number: 20080159176Abstract: A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.Type: ApplicationFiled: March 5, 2008Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Hume Heil, Michael Steven Siegel, Jeffrey R. Summers, Steven Paul VanderWiel
-
Publication number: 20070297441Abstract: In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventors: Timothy Hume Heil, Michael Steven Siegel, Jeffrey R. Summers, Steven Paul VanderWiel
-
Patent number: 6820174Abstract: In a multi-processor computer system, the processors are divided into broadcast groups and partition groups, with each processor belonging to exactly one broadcast group and exactly one partition group. Each processor holds a partition group directory indicative of contents of the caches associated with each other processor of the partition group. For read or write operations a processor broadcasts a message to other members of its broadcast group. The members of the broadcast group consult their respective partition directories to provide a complete response to a request for a needed item of data.Type: GrantFiled: January 18, 2002Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventor: Steven Paul Vanderwiel
-
Publication number: 20030140197Abstract: In a multi-processor computer system, the processors are divided into broadcast groups and partition groups, with each processor belonging to exactly one broadcast group and exactly one partition group. Each processor holds a partition group directory indicative of contents of the caches associated with each other processor of the partition group. For read or write operations a processor broadcasts a message to other members of its broadcast group. The members of the broadcast group consult their respective partition directories to provide a complete response to a request for a needed item of data.Type: ApplicationFiled: January 18, 2002Publication date: July 24, 2003Inventor: Steven Paul Vanderwiel