Patents by Inventor Steven R. A. Van Aerde
Steven R. A. Van Aerde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207309Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R.A. Van Aerde, Suvi Haukka, Atsuki Fukazawa, Hideaki Fukuda
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Patent number: 11610775Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.Type: GrantFiled: July 14, 2017Date of Patent: March 21, 2023Assignee: ASM IP Holding B.V.Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R. A. Van Aerde, Suvi Haukka, Atsuki Fukazawa, Hideaki Fukuda
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Publication number: 20210313167Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.Type: ApplicationFiled: July 14, 2017Publication date: October 7, 2021Inventors: Viljami PORE, Werner KNAEPEN, Bert JONGBLOED, Dieter PIERREUX, Steven R.A. van AERDE, Suvi HAUKKA, Atsuki FUKAZAWA, Hideaki FUKUDA
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Patent number: 10460932Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.Type: GrantFiled: March 31, 2017Date of Patent: October 29, 2019Assignee: ASM IP Holding B.V.Inventors: Steven R. A. Van Aerde, Kelly Houben, Maarten Stokhof, Bert Jongbloed, Dieter Pierreux
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Patent number: 10453685Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.Type: GrantFiled: March 31, 2017Date of Patent: October 22, 2019Assignee: ASM IP Holding B.V.Inventors: Kelly Houben, Steven R. A. Van Aerde, Maarten Stokhof, Bert Jongbloed, Dieter Pierreux, Werner Knaepen
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Publication number: 20180286672Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Steven R.A. Van Aerde, Kelly Houben, Maarten Stokhof, Bert Jongbloed, Dieter Pierreux
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Publication number: 20180286679Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Kelly Houben, Steven R.A. Van Aerde, Maarten Stokhof, Bert Jongbloed, Dieter Pierreux, Werner Knaepen
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Patent number: 9837271Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.Type: GrantFiled: November 13, 2015Date of Patent: December 5, 2017Assignee: ASM IP HOLDING B.V.Inventors: Steven R. A. Van Aerde, Cornelius A. van der Jeugd, Theodorus G. M. Oosterlaken, Frank Huussen
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Patent number: 9812320Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.Type: GrantFiled: July 28, 2016Date of Patent: November 7, 2017Assignee: ASM IP Holding B.V.Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R. A. Van Aerde, Suvi Haukka, Atsuki Fukuzawa, Hideaki Fukuda
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Patent number: 9443730Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.Type: GrantFiled: July 18, 2014Date of Patent: September 13, 2016Assignee: ASM IP Holding B.V.Inventors: Steven R. A. Van Aerde, Cornelius A. van der Jeugd, Theodorus G. M. Oosterlaken
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Publication number: 20160141176Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Steven R.A. Van Aerde, Cornelius A. van der Jeugd, Theodorus G.M. Oosterlaken, Frank Huussen
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Patent number: 9343304Abstract: An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or less is deposited on wafers accommodated in a wafer boat in a vertical furnace at a deposition temperature of the furnace while a deposition gas is flowing. During the first step, the temperature may be held substantially constant. In a second step, a temperature deviation or variation of at least 50° C. from the deposition temperature of the first step is applied and the furnace temperature is returned to the deposition temperature of the first step while the flow of the deposition gas is stopped. The first and second steps are repeated until a desired final film thickness is deposited.Type: GrantFiled: September 26, 2014Date of Patent: May 17, 2016Assignee: ASM IP HOLDING B.V.Inventors: Frank Huussen, Gijs Dingemans, Steven R. A. Van Aerde
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Publication number: 20160093487Abstract: An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or less is deposited on wafers accommodated in a wafer boat in a vertical furnace at a deposition temperature of the furnace while a deposition gas is flowing. During the first step, the temperature may be held substantially constant. In a second step, a temperature deviation or variation of at least 50° C. from the deposition temperature of the first step is applied and the furnace temperature is returned to the deposition temperature of the first step while the flow of the deposition gas is stopped. The first and second steps are repeated until a desired final film thickness is deposited.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Frank HUUSSEN, Gijs DINGEMANS, Steven R.A. Van Aerde
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Publication number: 20160020094Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.Type: ApplicationFiled: November 26, 2014Publication date: January 21, 2016Inventors: Steven R.A. Van Aerde, Cornelius A. van der Jeugd, Theodorus G.M. Oosterlaken
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Publication number: 20160020093Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.Type: ApplicationFiled: July 18, 2014Publication date: January 21, 2016Inventors: Steven R.A. Van Aerde, Cornelius A. van der Jeugd, Theodorus G.M. Oosterlaken
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Publication number: 20130269615Abstract: A wafer boat for holding a plurality of semiconductor wafers in a spaced apart relationship during processing, comprising at least one support member defining a plurality of sets of at least two vertically spaced apart wafer holding provisions, each of which wafer holding provisions is configured to independently hold a wafer in a substantially horizontal orientation, and wherein said sets are arranged such that the wafer boat is configured to accommodate a plurality of juxtaposed stacks of substantially horizontally oriented, vertically spaced apart wafers.Type: ApplicationFiled: April 16, 2012Publication date: October 17, 2013Applicant: ASM IP Holding B.V.Inventor: Steven R. A. Van Aerde
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Patent number: 8507388Abstract: In some embodiments, a reducing gas ambient containing a reducing agent is established in a batch process chamber before substrates are subjected to a deposition. The reducing atmosphere is established before and/or during loading of the substrates into the process chamber, and can include flowing reducing gas into the process chamber while the chamber is open. The reducing gas can be a mixture of a reducing agent and an inert gas, with the reducing agent being a minority component of the reducing gas. Using the reducing gas ambient, oxidation of substrate surfaces is reduced.Type: GrantFiled: April 26, 2010Date of Patent: August 13, 2013Assignee: ASM International N.V.Inventors: Steven R. A. Van Aerde, Rene de Blank
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Publication number: 20110263134Abstract: In some embodiments, a reducing gas ambient containing a reducing agent is established in a batch process chamber before substrates are subjected to a deposition. The reducing atmosphere is established before and/or during loading of the substrates into the process chamber, and can include flowing reducing gas into the process chamber while the chamber is open. The reducing gas can be a mixture of a reducing agent and an inert gas, with the reducing agent being a minority component of the reducing gas. Using the reducing gas ambient, oxidation of substrate surfaces is reduced.Type: ApplicationFiled: April 26, 2010Publication date: October 27, 2011Applicant: ASM INTERNALTIONAL N.V.Inventors: Steven R.A. Van Aerde, Rene de Blank
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Patent number: 7718518Abstract: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.Type: GrantFiled: December 14, 2006Date of Patent: May 18, 2010Assignee: ASM International N.V.Inventors: Peter Marc Zagwijn, Theodorus Gerardus Maria Oosterlaken, Steven R. A. Van Aerde, Pamela René Fischer
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Patent number: 7645486Abstract: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapor deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600° C. and 1200° C., for a duration between 10 minutes and 6 hours.Type: GrantFiled: February 22, 2007Date of Patent: January 12, 2010Assignees: S.O.I. Tec Silicon on Insulator Technologies, ASM International N.V.Inventors: Konstantin Bourdelle, Nicolas Daval, Ian Cayrefourcq, Steven R. A. Van Aerde, Marinus J. M. De Blank, Cornelius A. Van Der Jeugd