Abstract: A telecommunications system (18) is provided that includes a first controller (20) and a second controller (22) coupled using a packet-switched network (32). The controllers provide a low cost means of coupling isochronous telecommunication devices. The first controller (20) receives one or more isochronous input channels from a common control shelf (24), such as a private branch exchange (PBX), over a circuit-switched network (27). The first controller (20) encapsulates an isochronous frames from the common control shelf (27) into a data frame that is transferrable over the packet-switched network (32). The second controller (22) is configured to receive the data frame and extract the isochronous frame, which is then transmitted to a peripheral shelf (26), such as a line trunk unit (LTU), using an isochronous circuit-switched network (38). The controllers contain identical functionality, permitting bi-directional transmission of data between the common control and peripheral shelves.

Abstract: Signal transmission systems for second and third generation mobile communications networks are described. A signal distribution system comprises a plurality of rf transmitters for serving a plurality of network cells. The system is characterised by a multiplexer coupled to the transmitters for multiplexing the transmitter outputs, a signal transporter for transporting the multiplexed signals to each of the network cells, and a multiplexed signal receiver at each cell for selecting and receiving a signal from a transmitter serving the cell. The invention also provides a complementary signal reception system, and corresponding methods. Preferably, the multiplexed signals are transported over a fibre optic network such as an existing cable TV network. The system simplifies the deployment of network infrastructure for third generation mobile communications systems.

Abstract: A synchronization circuit (30) includes three flip-flops responsive to a common clock signal (CLK2). The input to the first flip-flop (32) represents the least significant bit (LSB) of a counter (31) included within a first clock domain. The CLK2 signal originates from a second clock domain. The output of the first flip-flop is provided as input to the second flip-flop (34), and the second flip-flop output is provided as input to the third flip-flop (36). An exclusive-or (XOR) gate (38) generates a synchronization signal in response to outputs of the second and third flip-flops (34-36). The synchronization signal is usable within the second clock domain and activate for one period of CLK2 subsequent to every transition occurring on the LSB input. The active state of the synchronization signal indicates that a predefined set of data inputs is stable and valid. In this manner, a single unsynchronized input signal, i.e., the LSB input, can be used to synchronize the data inputs.

Abstract: A method of automatically selecting a mode of operation during an initialization sequence of a multi-mode signal controller includes selectively enabling and disabling signal reception and signal driving capabilities and includes monitoring the remaining signal traffic to determine the position of the controller along a communication path. In the preferred embodiment, the signal controller is one of at least two identical signal controllers along a single communication path. For example, the controllers may be components at opposite sides of a telecommunications link of a PBX or other telecommunication system. The structurally identical controllers perform mirror image operations when the controllers are properly initialized to restrict the controllers to different modes of operation. In the initialization sequence for a particular signal controller, the signal reception is monitored to determine whether the controller is receiving a known pattern of system control, such as a universally applied clock signal.

Abstract: A method and system of enabling intra-system communication between first and second microprocessors in an asynchronous transfer mode (ATM) environment includes emulating ATM segmentation and reassembly at the first microprocessor. The second microprocessor is connected to circuitry for supporting ATM communications with other systems. With respect to an inter-processor communication (IPC) from the first microprocessor to the second microprocessor, conventional ATM segmentation is emulated at the first microprocessor, thereby forming fixed-length cells having payloads representative of the IPC. ATM-compatible header information is attached to each one of the cells and transferred to the circuitry, which typically includes a segmentation and reassembly (SAR) device. The circuitry reassembles the message and forwards the IPC to the second microprocessor.

Abstract: A header machine for drilling specified hole patterns in pipe and for cutting the pipe to a specified length to form headers for use in heat transfer products. The header machine includes hold clamps for selectively holding the pipe during the processing of the pipe and feed clamps for selectively holding the pipe during the feeding thereof through the header machine. The feed clamps are mounted on a feed carriage which is movably mounted for movement forwardly and rearwardly. The feed carriage is driven by a stepper motor operably coupled to the feed carriage for moving the feed carriage and the pipe endwise to various drilling positions. The header machine also includes a spud drill for drilling spud holes in the pipe, a connection drill for drilling connection holes in the pipe, a circular saw for cutting the pipe to a specified length, and provisions for making double circuit patterns of the spud hole.