Abstract: Bitmap compression for fast searches and updates is provided. Compressing a bitmap includes receiving a bitmap to compress, and reading the bitmap to determine a value of a bit location for all bits in the bitmap. In one embodiment, a compressed bitmap is created by encoding a variable number of bytes to represent a distance between adjacent 1s in the uncompressed bitmap. In another embodiment, a compressed bitmap is created by representing a distance between adjacent 1s in the uncompressed bitmap using a plurality of bits, and encoding a marker word to indicate the number of bits used to represent the distance.

Abstract: A system includes a tape support surface configured to receive a plurality of tape spools, and a plurality of robotic accessors capable of picking the tape spools from the tape support surface, transporting the tape spools, and releasing the tape spools at a drop location. The accessors are capable of passing each other during the transporting. Another system includes a first tape support surface configured to receive a plurality of tape spools, a second tape support surface facing the first tape support surface, and a plurality of robotic accessors capable of picking the tape spools from the tape support surface, transporting the tape spools, and releasing the tape spools at a drop location. At least one of the accessors is capable of picking tape spools from both tape support surfaces.

Abstract: Embodiments of the invention relate to tape drive systems having overlapped operations. In one aspect, a system includes a head for performing read and/or write operations, a first set of motors for performing positioning operations on a first tape, a second set of motors for performing positioning operations on a second tape, and a processor and logic integrated with and/or executable by the processor. The logic is configured to cause the first set of motors to pass the first tape over the head while causing the second set of motors to perform at least one of a coarse locate and a rewind operation on the second tape. Additional systems and methods are also disclosed.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr?1 erasures in any one of the remaining r?1 rows, up to tr?2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.

Abstract: Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe.

Abstract: A system includes a linear storage media tier; a second storage tier having higher performance than the linear storage media tier; a data controller for moving data between the tiers; and a host interface responsive to disk and/or network storage commands. The linear storage media tier includes: a rest area for storing reels having linear media thereon, at least one linear media drive configured for reading and/or writing the linear media, and at least one robot for transporting the linear storage media between the rest area and the at least one linear media drive. The robot moves along a first surface via contact with the surface. A system according to another embodiment includes a linear storage media tier characterized by having a read access time to any block of data stored on any reel in the rest area in less than 10 seconds.

Abstract: Aspects of the present invention include a system, method, and computer program product for skewing expected wearout times of memory devices in an array are provided according to some embodiments of the present invention. In general, the method includes determining or receiving an amount of spare space to provide in an array of memory devices, allocating the spare space non-uniformly to the memory devices in the array, and skewing expected wearout times of the memory devices by controlling writing of data to the array according to the allocation of the spare space.

Abstract: Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

Abstract: Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

Abstract: Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller.

Abstract: Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr?1 erasures in any one of the remaining r?1 rows, up to tr?2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.

Abstract: Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r-1 rows, up to tr-2 erasures in any one of the remaining r-2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.

Abstract: Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

Abstract: Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

Abstract: Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r?1 rows, up to tr-2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.