Patents by Inventor Steven R. Hutsell
Steven R. Hutsell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947457Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: GrantFiled: November 22, 2022Date of Patent: April 2, 2024Assignee: Apple Inc.Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Patent number: 11934265Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.Type: GrantFiled: June 1, 2022Date of Patent: March 19, 2024Assignee: Apple Inc.Inventors: Farid Nemati, Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, James Vash, Era K. Nangia, Gregory S. Mathews
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Patent number: 11934313Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.Type: GrantFiled: August 22, 2022Date of Patent: March 19, 2024Assignee: Apple Inc.Inventors: Per H. Hammarlund, Lior Zimet, James Vash, Gaurav Garg, Sergio Kolor, Harshavardhan Kaushikkar, Ramesh B. Gunna, Steven R. Hutsell
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Patent number: 11868258Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: GrantFiled: January 27, 2023Date of Patent: January 9, 2024Assignee: Apple Inc.Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Patent number: 11829242Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.Type: GrantFiled: June 1, 2022Date of Patent: November 28, 2023Assignee: Apple Inc.Inventors: Farid Nemati, Steven R. Hutsell, Gregory S. Mathews, Yi Chun Chen, Kevin C. Wong, Kalpana Bansal
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Publication number: 20230350828Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: ApplicationFiled: April 28, 2023Publication date: November 2, 2023Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Publication number: 20230325274Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.Type: ApplicationFiled: May 24, 2023Publication date: October 12, 2023Inventors: Farid Nemati, Steven R. Hutsell, Gregory S. Mathews, Yi Chun Chen, Kevin C. Wong, Kalpana Bansal
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Publication number: 20230305924Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.Type: ApplicationFiled: June 1, 2022Publication date: September 28, 2023Inventors: Farid Nemati, Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, James Vash, Era K. Nangia, Gregory S. Mathews
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Publication number: 20230251930Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.Type: ApplicationFiled: June 1, 2022Publication date: August 10, 2023Inventors: Farid Nemati, Steven R. Hutsell, Gregory S. Mathews, Yi Chun Chen, Kevin C. Wong, Kalpana Bansal
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Patent number: 11675722Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Publication number: 20230169003Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: ApplicationFiled: January 27, 2023Publication date: June 1, 2023Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Publication number: 20230083397Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: ApplicationFiled: November 22, 2022Publication date: March 16, 2023Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Publication number: 20230053530Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota, Sagi Lahav, James Vash, Gaurav Garg, Jonathan M. Redshaw, Steven R. Hutsell, Harshavardhan Kaushikkar, Shawn M. Fukami
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Publication number: 20230056044Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Lior Zimet, James Vash, Gaurav Garg, Sergio Kolor, Harshavardhan Kaushikkar, Ramesh B. Gunna, Steven R. Hutsell
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Patent number: 11544193Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: GrantFiled: May 10, 2021Date of Patent: January 3, 2023Assignee: Apple Inc.Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Publication number: 20220083472Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: ApplicationFiled: May 10, 2021Publication date: March 17, 2022Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund
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Publication number: 20160224252Abstract: Hybrid memory architecture technologies are described. In accordance with embodiments disclosed herein, there is provided a processing device having a core and a memory controller communicably coupled to the core to receive a request to fetch data. The memory controller is communicably coupled to a hybrid memory architecture including a near memory, wherein the near memory is divided into a flat memory region and a cache memory region.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: Steven R. Hutsell, Rajat Agarwal, Avinash Sodani, Darrell S. McGinnis
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Patent number: 7971074Abstract: A system and method to provide source controlled dynamic power management. An activity detector in a source determines expected future resource usage. Based on that expected usage, the source generates a power management command and sends that command to a destination. The destination then adjusts the power level of the resource based in the command.Type: GrantFiled: June 28, 2007Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Yen-Cheng Liu, Steven R. Hutsell, Krishnakanth Sistla
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Patent number: 7827425Abstract: A system and method to provide source controlled dynamic power management. An activity detector in a source determines expected future resource usage. Based on that expected usage, the source generates a power management command and sends that command to a destination. The destination then adjusts the power level of the resource based in the command.Type: GrantFiled: June 29, 2006Date of Patent: November 2, 2010Assignee: Intel CorporationInventors: Steven R. Hutsell, Krishnakanth Sistla, Yen-cheng Liu
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Patent number: 7730266Abstract: Snoop filtering methods and apparatuses for systems utilizing memory are contemplated. Method embodiments comprise receiving a request for contents of a memory line by a home agent, comparing an address of the memory line to a range in a set of adaptive ranges, and snooping an I/O agent for the contents upon a match of the address within the range. Apparatus embodiments comprise a range table, a table updater, a receiver module, and a range comparator. The range tables allow for the tracking of memory addresses as I/O agents assert ownership of the addresses. Employing a range-based snoop filtering approach may allow home agents to track a collection of addresses, in adaptable ranges, instead of tracking precise addresses which may require large quantities of memory to implement.Type: GrantFiled: March 31, 2007Date of Patent: June 1, 2010Assignee: Intel CorporationInventors: Krishnakanth Sistla, Steven R. Hutsell