Abstract: A mechanism for 1:1, 1+1, and UPSR path-switched protection switching, particularly for optical interface units in synchronous optical network (SONET) multiplexer equipment. A working unit and a standby unit pair protect each other in the event of a failure of the working unit or the failure of the span connected to the working unit if both the working and standby units are connected to different spans. Each unit is made responsible for detecting failures of the span that it receives and is primarily responsible for detecting a fault within the unit's own hardware or software. When a unit or span failure is detected, switch control is localized to the two units (i.e. the working and standby unit) which eliminates the need for a third control unit, which reduces processing time and reduces the system hardware.

Abstract: In a telephone system having multiple working metallic interface units, a method and a structure provide protection by assigning to each metallic interface unit a partner unit, which is another metallic interface unit. Under this arrangement, when a failure occurs in a working metallic interface unit, its partner unit switches the ring/tip input signals of the failed metallic interface unit to a protection bus. A standby or protective unit then takes over by receiving the rerouted tip/ring signals from the protection bus. The failed working unit can then be removed from the shelf without disrupting service.

Abstract: An interface device is provided which may be used to perform rate adaptation and time slot assignment, in either the transmit or receive directions, in a multiplexing unit for interfacing a high rate optical carrier line to a plurality of lower rate information carrier lines. The high rate optical carrier line may be a SONET or SDH carrier line. The interface device according to the present invention may be operationally configured to provide data rate adaptation and time slot assignment between an optical carrier line operating at an OC-12 rate with lower rate lines operating according to OC-3, OC-1, DS-3, or DS-1 protocols, or even virtual channels. A plurality of identical interface devices may be cascaded together and used to perform interface support for various channels operating at various rates, merely by manipulating the operational configuration of the individual interface devices in the cascade.

Abstract: A universal tributary interface group approach for SONET multiplex equipment in which the shelf is partitioned into regions and each region can be provisioned to support different service types. The universal tributary group system includes an equipment shelf having a backplane. The equipment shelf is partitioned into regions called tributary groups which are each capable of accepting tributary units having compatible bus widths and clock rates. Removable card guides may be inserted into the tributary group spaces so that tributary interface units of different heights and widths may be placed in the tributary group spaces. Additionally, a plurality of bus segments run along the backplane to electrically connect a time slot interchange unit to card slots in the tributary groups. Each of the bus segments is capable of being provisioned to use a bus rate compatible with the data requirements of the tributary group it services.

Abstract: A method for fault coverage testing an integrated circuit having a memory device with word locations, including the steps of setting test data to an initial value, dependently making the test data unique for each of the word locations, and automatically, dependently testing each bit of each of the word locations for a fault using the unique test data which corresponds to the word location being tested. Alternatively, the method may include the steps of inverting a bit of test data, writing the test data to a current word location of the memory device, reading test data from the current word location of the memory device, rotating the test data read by one bit position, repeating the writing, reading and rotating a predetermined number of times for each of the word locations, and comparing the test data read from a last word location of the memory device with a predetermined value. A system for performing the fault coverage testing method is also disclosed.

Abstract: A Coded Marked Inversion (CMI) encoding circuit having a completely synchronous and digital implementation for encoding a stream of digital data in non-return-to-zero (NRZ) format into the CMI format. The encoding circuit includes a clock for providing a clock signal having a certain period, an input circuit for obtaining two samples of the NRZ data during each clock period, and a state machine which, in response to the two samples of the NRZ data, produces CMI encoded data. In a more advanced implementation, the encoding circuit includes error encoding circuitry for detecting errors in the incoming samples of NRZ data. The encoding circuit then outputs data indicative of the rate at which errors are received.

Abstract: A method for transporting common control data on a backplane bus under the SONET standard uses the section and line overhead bytes. A unit is assigned a predefined number of time slots during in the STS-1 synchronous payload envelope to assert a data transmission request on a request/acknowledge bus. Each unit keeps queue and count-down counters for monitoring, respectively, the total number of pending packets in the system and the number of packets ahead of the unit's own queued transmission. This method is implemented on a PCM bus using a transmission circuit and a receiving circuit.

Abstract: A telecommunication network which includes a SONET-based digital subscriber loop carrier system that supports wideband and narrowband services. The digital subscriber loop carrier system includes a common module for performing common functions of the system and for transferring subscriber data between the system and a central office or local digital switch, and at least one service definition module, which is coupled to subscribers, for interfacing the subscribers to the system. The common module and the service definition modules are coupled by a common backplane including pulse coded modulation buses and all data, including both subscriber data and control data, are transferred per the SONET protocol. Each of the common module and service definition modules employ buses, which are also based on the SONET protocol.

Abstract: A method and digital circuit for decoding and recovering a data clock from an incoming stream of Coded Marked Inversion (CMI) encoded data. The CMI encoded data is applied to a shift register where the data is sampled at a rate greater than the incoming transfer rate thus providing multiple samples per data period. The multiple samples having a high logical value occuring during the first half of a data period are counted and a represented value is outputted. The multiple samples having a high logical value occurring during the second half of the data period are also counted and a second represented value is outputted. The two represented values are compared and a single CMI-decoded data bit is determined. The multiple samples are also compared to detect a high-to-low transition which, according to the CMI format, constitutes a data boundary. First and second free-running counters are provided, whose most significant output bits provide an initial clock signal and a recovered data clock, respectively.

Abstract: A multiplexing communications system comprising a first terminal means for transmitting and receiving user digitized data, a second terminal means for transmitting and receiving the user digitized data, and a communications link means for conveying the user digitized data in either direction between the first terminal means and the second terminal means. The first terminal means maintains a copy of digital control data which is necessary for controlling the second terminal means. The first terminal means has first download means for transmitting this digital control data to the second terminal means via the communications link means. The second terminal means contains a memory means for storing the digital control data, and control means for controlling the second terminal means during its normal transmitting and receiving operations. The control means requires that the digital control data be accessible from the memory means.

Abstract: A circuit having a completely synchronous and digital implementation for encoding a stream of digital data (NRZ form) into the coded marked inversion (CMI) format. The circuit includes a state machine having a predetermined number of defined legal and illegal states, an illegal state detection circuit, and an output circuit. When the state machine enters an illegal state because of, for example, the effects of noise or distortion on the digital data signal, the illegal state detection circuit forces the state machine back into a legal state.

Abstract: A circuit and method for more efficiently implementing ZBTSI encoding with minimum processing delay of the ZBTSI algorithm and hardware complexity is provided in a ZBTSI encoder for use in a ZBTSI codec. The ZBTSI encoder is optimized for the ZBTSI algorithm and includes an architecture for use as an improved ZBTSI codec in application-specific integrated circuit (ASIC) technology.

Abstract: A Violating All Zero Octet (VAZO) detector for a ZBTSI clear channel data transmission system is described, which is optimized for minimum logic gate count, minimum circuit complexity, minimum external control signals and minimum signal processing delay, in a VLSI hardware embodiment which is advantageously implemented in application specific integrated circuit (ASIC) technology. An array of logic NOR gates scans input data for zero strings of data that could combine with an all-zero octet to violate the zero string criterion enables a zero string search to be performed with a minimum of circuit complexity. The use of an input shift register to buffer input data for other portions of the associated ZBTSI encoder provides for a minimized number of gates in a VLSI implementation.

Abstract: A method and circuit for exploiting the characteristics of the ZBTSI algorithm by using the relationship of the data octet and the octets adjacent thereto to detect error conditions such as violations of the DS1 ones density criteria for detection of transmission channel errors in the ZBTSI decoder. This relationship provides an optimized partial error correction technique which minimizes error multiplication in the PCM transmission channels.