Abstract: Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process.

Abstract: A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased.

Abstract: Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process.

Abstract: A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased.