Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.

Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.

Abstract: One illustrative MRAM device disclosed herein includes a first bit cell and a second bit cell. The first bit cell comprises a first access transistor and a first MTJ stack. The first MTJ stack comprises a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor. The second bit cell comprises a second access transistor and a second MTJ stack. The second MTJ stack comprises a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

Abstract: The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure.

Abstract: The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Abstract: The present disclosure is directed to various embodiments of a method for forming replacement gate structures for vertical transistors.

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.