Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.

Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes several nodes that represent IC components. The method identifies a path in the graph that starts from a timed source node and ends at a timed target node. The path has several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to a set of clocked elements without changing the position of any clocked element relative to the position of the computational elements in the path. The clock signal of at least one clocked element is skewed by more than a period of the clock signal. The method implements the IC design by using the optimized IC design.

Abstract: A method of optimizing timing performance of an IC design expressed as a graph that includes several nodes representing IC components is provided. The method identifies several paths in the graph. Each path starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths to satisfy timing constraints. The method identifies a path that includes a set of edge-triggered clocked elements and does not satisfy the set of timing constraints. The method replaces each edge-triggered clocked element in the identified path with a level-sensitive clocked element and optimizes the timing performance of the IC design by skewing clock signals one or more clocked element in the identified path.

Abstract: A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use.

Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.

Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Abstract: Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable storage element includes a parallel distributed path for configurably providing a pair of transparent storage elements. The pair of configurable storage elements can configurably act either as non-transparent (i.e., clocked) storage elements or transparent configurable storage elements. In some embodiments, the configurable storage element in the routing fabric performs both routing and storage operations by a parallel distributed path that includes a clocked storage element and a bypass connection. In some embodiments, the configurable storage element perform both routing and storage operations by a pair of master-slave latches but without a bypass connection.

Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Abstract: A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

Abstract: A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design and uses a satisfiability solver to resolve placement violations. In some embodiments, the constraints include mathematical expressions that express timing requirements. The method in some embodiments converts the mathematical expressions into Boolean clauses and sends the clauses to a satisfiability solver that is only capable of solving Boolean clauses. In some embodiments, the method groups several cells in the user design and several sites on the IC fabric and uses the satisfiability solver to resolve all placement issues in the group. The satisfiability solver informs placer after each cell is moved to a different site. The method then dynamically builds more constraints based on the new cell placement and sends the constraints to the satisfiability solver.

Abstract: An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.

Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.

Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

Abstract: A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use.