Patents by Inventor Steven Thijs
Steven Thijs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8508893Abstract: An distributed electronic circuit (1), such as a transmission line or distributed amplifier, is disclosed comprising an input terminal (2), an output terminal (3), power supply lines (4,5), a sequence of sections (61, 62, 63, 64, 65), between the input terminal (2) and the output terminal (3), arranged to transfer an electrical signal from one section to another section; each section (61, 62, 63, 64, 65) comprising at least one Electro Static Discharge (ESD) protection component (9) configured to, upon occurrence of an ESD event, convey corresponding ESD currents to a power supply line (4, 5); and wherein the ESD components (9) of the respective sections (61, 62, 63, 64, 65) are selected such that, upon occurrence of an ESD event, at least one subsequent section (62, 63, 64, 65) is triggered before the first section (61).Type: GrantFiled: August 26, 2010Date of Patent: August 13, 2013Assignee: IMECInventors: Steven Thijs, Dimitri Linten
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Patent number: 8143700Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.Type: GrantFiled: December 29, 2008Date of Patent: March 27, 2012Assignee: Sofics BVBAInventors: Pieter Vanysacker, Benjamin Van Camp, Olivier Marichal, Wybo Geert, Steven Thijs, Gerd Vermont
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Patent number: 7923266Abstract: A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.Type: GrantFiled: May 7, 2009Date of Patent: April 12, 2011Assignee: IMECInventors: Steven Thijs, Dimitri Linten, David Eric Trémouilles
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Publication number: 20110051301Abstract: A method for designing an integrated electronic circuit (1) having Electro Static Discharge (ESD) protection, the method comprising providing an integrated electronic circuit (1) having a predetermined performance during normal operation of the circuit, the integrated electronic circuit (1) comprising a power supply line (2) and at least one active device (4) protected by an ESD protection device (5), the active device (4) being powered from the power supply line (2), simulating an ESD event on the integrated electronic circuit (1) to determine if and where, during the ESD event, a parasitic ESD current path is created between the power supply line (2) and the at least one active device (4), and creating in thus determined parasitic ESD current path a circuit (6) to interrupt this parasitic ESD current path, at least during part of the ESD event.Type: ApplicationFiled: August 26, 2010Publication date: March 3, 2011Applicant: IMECInventors: Steven Thijs, Dimitri Linten
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Publication number: 20110051300Abstract: An distributed electronic circuit (1), such as a transmission line or distributed amplifier, is disclosed comprising an input terminal (2), an output terminal (3), power supply lines (4,5), a sequence of sections (61, 62, 63, 64, 65), between the input terminal (2) and the output terminal (3), arranged to transfer an electrical signal from one section to another section; each section (61, 62, 63, 64, 65) comprising at least one Electro Static Discharge (ESD) protection component (9) configured to, upon occurrence of an ESD event, convey corresponding ESD currents to a power supply line (4, 5); and wherein the ESD components (9) of the respective sections (61, 62, 63, 64, 65) are selected such that, upon occurrence of an ESD event, at least one subsequent section (62, 63, 64, 65) is triggered before the first section (61).Type: ApplicationFiled: August 26, 2010Publication date: March 3, 2011Applicant: IMECInventors: Steven Thijs, Dimitri Linten
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Patent number: 7821272Abstract: The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method includes the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances.Type: GrantFiled: March 19, 2008Date of Patent: October 26, 2010Assignee: IMECInventors: Mirko Scholz, David Eric Tremouilles, Steven Thijs, Dimitri Linten
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Publication number: 20100142105Abstract: The disclosed method and device relates to a bidirectional ESD power clamp, comprising a semiconductor structure (BigNFET; BigPFET) having a conductive path connected between first and second nodes and having a triggering node via which the conductive path can be triggered. An ESD transient detection circuit is connected between the first and second nodes and to the triggering node and comprises a first part for detecting an occurrence of a first ESD transient on the first node. The semiconductor structure is provided on an insulator substrate, such that a parasitic conductive path between said first and second nodes via the substrate is avoided. The ESD transient detection circuit further comprises a second part for detecting an occurrence of a second ESD transient on the second node.Type: ApplicationFiled: December 3, 2009Publication date: June 10, 2010Applicant: IMECInventors: Dimitri Linten, Steven Thijs, David Eric Tremouilles, Natarajan Mahadeva Iyer
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Patent number: 7687859Abstract: An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.Type: GrantFiled: September 7, 2007Date of Patent: March 30, 2010Assignees: Infineon Technologies AG, IMEC VZW.Inventors: Christian Russ, David Trémouilles, Steven Thijs
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Patent number: 7649722Abstract: A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.Type: GrantFiled: September 14, 2006Date of Patent: January 19, 2010Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Steven Thijs, Natarajan Mahadeva Iyer, Dimitri Linten
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Publication number: 20090280582Abstract: A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.Type: ApplicationFiled: May 7, 2009Publication date: November 12, 2009Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUMInventors: Steven Thijs, Dimitri Linten, David Eric Tremouilles
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Publication number: 20090101938Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.Type: ApplicationFiled: December 29, 2008Publication date: April 23, 2009Applicants: SARNOFF CORPORATION, SARNOFF EUROPEInventors: Pieter Vanysacker, Benjamin Van Camp, Olivier Marichal, Wybo Geert, Steven Thijs, Gerd Vermont
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Publication number: 20090073621Abstract: A method and apparatus for designing an ESD protection circuit comprising a main ESD device and a triggering device connected to a triggering node of the main ESD device by means of which the main ESD device can be triggered for conducting ESD current at a reduced voltage. The triggering device is located in an initial current path for the ESD current. In this initial current path, there is at least one triggering component which can be triggered from an off-state to an on-state. The triggering speed of this component is considered and its design is optimised in view of increasing its triggering speed. Further shown is an ESD protection circuit in which at least one triggering component is selected to be of a predetermined type for achieving a fast triggering speed, preferably of the gated diode type.Type: ApplicationFiled: September 12, 2008Publication date: March 19, 2009Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Steven Thijs, David Eric Tremouilles
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Publication number: 20090065868Abstract: An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.Type: ApplicationFiled: September 7, 2007Publication date: March 12, 2009Inventors: Christian Russ, David Tremouilles, Steven Thijs
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Publication number: 20090027063Abstract: The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method comprises the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances.Type: ApplicationFiled: March 19, 2008Publication date: January 29, 2009Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), HANWA ELECTRONICS IND. CO., LTD.Inventors: Mirko Scholz, David Eric Tremouilles, Steven Thijs, Dimitri Linten
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Publication number: 20070247772Abstract: The present invention provides an improvement on ESD protection circuitry by controlling the trigger circuit to prevent the unwanted triggering of the device. The circuitry includes an ESD clamp with a trigger circuit coupled to the clamp. Both the clamp and the trigger circuit are coupled to a first reference potential. The circuitry also includes a control line coupled to the trigger circuit. The control line is coupled to a second reference potential to further control the behavior of the trigger circuit such that when the power is supplied to the second reference potential, the control line disables the trigger circuit, and when power is not supplied to the second reference potential, the control line enables the trigger circuit.Type: ApplicationFiled: April 19, 2007Publication date: October 25, 2007Applicants: SARNOFF CORPORATION, SARNOFF EUROPE BVBAInventors: Bart Keppens, Benjamin Van Camp, Aagje Bens, Pieter Vanysacker, Steven Thijs
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Publication number: 20070058308Abstract: A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.Type: ApplicationFiled: September 14, 2006Publication date: March 15, 2007Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Steven Thijs, Natarajan Mahadeva Iyer, Dimitri Linten
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Patent number: 7181352Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.Type: GrantFiled: April 2, 2004Date of Patent: February 20, 2007Assignee: Interuniversitaire Microelektronica Centrum (IMEC) vzwInventors: Natarajan Mahadeva Iyer, Steven Thijs, Vesselin K. Vassilev, Tom Daenen, Vincent De Heyn
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Publication number: 20070002508Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.Type: ApplicationFiled: March 30, 2006Publication date: January 4, 2007Inventors: Pieter Vanysacker, Benjamin Van Camp, Olivier Marichal, Wybo Geert, Steven Thijs, Gerd Vermont
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Publication number: 20040239346Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.Type: ApplicationFiled: April 2, 2004Publication date: December 2, 2004Inventors: Natarajan Mahadeva Iyer, Steven Thijs, Vesselin K. Vassilev, Tom Daenen, Vincent De Heyn