Patents by Inventor Steven Thomas Peake
Steven Thomas Peake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10153365Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.Type: GrantFiled: August 10, 2016Date of Patent: December 11, 2018Assignee: Nexperia B.V.Inventors: Steven Thomas Peake, Philip Rutter, Chris Rogers
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Patent number: 10032907Abstract: A device is disclosed. The device comprises a substrate having an epitaxial layer of a first conductivity type, a deep trench of a first depth, a pillar region of a second conductivity type of a second depth and a blocking layer of a third conductivity type immediately below a bottom surface of the deep trench. The second depth is larger than the first depth.Type: GrantFiled: October 4, 2016Date of Patent: July 24, 2018Assignee: Nexperia B.V.Inventor: Steven Thomas Peake
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Patent number: 9985092Abstract: A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a first vertical section of a second conductivity type in the expitaxial layer, creating a first vertical trench through etching vertically next to the first vertical section, filling the first vertical trench with a first type oxide, forming a second vertical trench in the first vertical trench. The second vertical trench is bounded by the first type oxide in the first vertical trench. The process further includes forming a second type oxide on inner walls of the second vertical trench, filling the second vertical trench with polysilicon. In a second vertical section of the epitaxial layer vertically next to the first vertical trench, a body region is created by implanting ions of the first conductivity type and a source region is created by implanting ions in a top layer of the body region.Type: GrantFiled: September 13, 2016Date of Patent: May 29, 2018Assignee: Nexperia B.V.Inventor: Steven Thomas Peake
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Patent number: 9941265Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.Type: GrantFiled: July 1, 2016Date of Patent: April 10, 2018Assignee: Nexperia B.V.Inventors: Philip Rutter, Jan Sonsky, Barry Wynne, Yan Lai, Steven Thomas Peake
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Publication number: 20180097105Abstract: A device is disclosed. The device comprises a substrate having an epitaxial layer of a first conductivity type, a deep trench of a first depth, a pillar region of a second conductivity type of a second depth and a blocking layer of a third conductivity type immediately below a bottom surface of the deep trench. The second depth is larger than the first depth.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Inventor: Steven Thomas Peake
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Publication number: 20180076279Abstract: A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a first vertical section of a second conductivity type in the expitaxial layer, creating a first vertical trench through etching vertically next to the first vertical section, filling the first vertical trench with a first type oxide, forming a second vertical trench in the first vertical trench. The second vertical trench is bounded by the first type oxide in the first vertical trench. The process further includes forming a second type oxide on inner walls of the second vertical trench, filling the second vertical trench with polysilicon. In a second vertical section of the epitaxial layer vertically next to the first vertical trench, a body region is created by implanting ions of the first conductivity type and a source region is created by implanting ions in a top layer of the body region.Type: ApplicationFiled: September 13, 2016Publication date: March 15, 2018Inventor: Steven Thomas Peake
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Publication number: 20180006015Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: Philip Rutter, Jan Sonsky, Barry Wynne, Yan Lai, Steven Thomas Peake
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Patent number: 9735254Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.Type: GrantFiled: March 11, 2015Date of Patent: August 15, 2017Assignee: Nexperia B.V.Inventors: Steven Thomas Peake, Philip Rutter
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Publication number: 20170077291Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.Type: ApplicationFiled: August 10, 2016Publication date: March 16, 2017Inventors: Steven Thomas Peake, Philip Rutter, Chris Rogers
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Patent number: 9570605Abstract: A device is disclosed. The device includes a semiconductor substrate, a plurality of source lines formed on a surface of the semiconductor substrate. The plurality of source lines are laid in both X and Y directions. The device further includes a plurality of gate lines laid out over source lines in X direction in the plurality of source lines, a source contact line that connects source lines in the plurality of source lines that are terminating in Y direction, a gate contact line that connects the plurality of gate lines and a drain contact.Type: GrantFiled: May 9, 2016Date of Patent: February 14, 2017Assignee: NXP B.V.Inventor: Steven Thomas Peake
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Publication number: 20150187913Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Steven Thomas Peake, Philip Rutter
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Patent number: 9048116Abstract: A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes.Type: GrantFiled: November 21, 2012Date of Patent: June 2, 2015Assignee: NXP B.V.Inventors: Phil Rutter, Ian Culshaw, Steven Thomas Peake
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Patent number: 9006822Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.Type: GrantFiled: October 24, 2012Date of Patent: April 14, 2015Assignee: NXP B.V.Inventors: Steven Thomas Peake, Phil Rutter
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Patent number: 8901638Abstract: A trench-gate semiconductor device is disclosed, in which the player (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The replacement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region.Type: GrantFiled: July 27, 2009Date of Patent: December 2, 2014Assignee: NXP B.V.Inventors: Steven Thomas Peake, Phil Rutter
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Patent number: 8513733Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.Type: GrantFiled: August 15, 2011Date of Patent: August 20, 2013Assignee: NXP B.V.Inventors: Steven Thomas Peake, Philip Rutter
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Patent number: 8357971Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.Type: GrantFiled: October 22, 2008Date of Patent: January 22, 2013Assignee: NXP B.V.Inventors: Steven Thomas Peake, Philip Rutter, Christopher Martin Rogers, Miron Drobnis, Andrew Butler
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Publication number: 20120037980Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.Type: ApplicationFiled: August 15, 2011Publication date: February 16, 2012Applicant: NXP B.V.Inventors: Steven Thomas Peake, Philip Rutter
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Publication number: 20110121384Abstract: A trench-gate semiconductor device is disclosed, in which the p-layer (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The re-placement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region.Type: ApplicationFiled: July 27, 2009Publication date: May 26, 2011Applicant: NXP B.V.Inventors: Steven Thomas Peake, Phil Rutter
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Publication number: 20100320532Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.Type: ApplicationFiled: October 22, 2008Publication date: December 23, 2010Applicant: NXP B.V.Inventors: Steven Thomas Peake, Philip Rutter, Christopher Martin Rogers, Miron Drobnis, Andrew Butler
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Patent number: 6979865Abstract: A cellular MOSFET device has a cellular area (CA) comprising active MOSFET cells, and one or more Schottky diode areas (SA) accommodated within a deep end region (15) at a lateral boundary of this cellular area (CA). This deep end region (150) is laterally divided so as to accommodate the diode area (SA) therein. A diode portion (14d) of the first conductivity type of the drain region (14) extends upwardly through the laterally-divided deep end region (150) that is of the second conductivity type. The Schotty barrier (100) formed with this diode portion (14d) terminates laterally in the laterally-divided portions (150deep end region (150) which serve as a guard region and field-relief region for the Schottky diode.Type: GrantFiled: January 23, 2003Date of Patent: December 27, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Steven Thomas Peake, Christopher Martin Rogers