Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Abstract: Methods and apparatus to optically couple an optoelectronic chip to a waveguide are disclosed. A disclosed apparatus includes a substrate, a waveguide mounted on the substrate and an optoelectronic chip bonded to the substrate and having an optical element directly engaging the waveguide.

Abstract: An apparatus comprising a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, a die including an optical area, the die being flip-chip bonded to the substrate, and an optical inter-connector optically coupled to the optical area and at least partially positioned between the die and the base substrate, the optical inter-connector positioned in a trench formed in the solder resist layer and the conductive layer. A process comprising providing a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, forming a trench in the conductive layer and the solder resist layer, positioning a waveguide in the trench, and flip-chip bonding a die to the substrate, the die including an optical area, such that the optical area is optically coupled to the waveguide.

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: Optical apparatus, methods of forming the apparatus, and methods of using the apparatus are disclosed herein. In one aspect, an optical apparatus may include a substrate, an on-substrate microlens coupled with the substrate to receive light from an off-substrate light emitter and focus the light toward a focal point, and an on-substrate optical device coupled with the substrate proximate the focal point to receive the focused light. Communication of light in the reverse direction is also disclosed. Systems including the optical apparatus are also disclosed.

Abstract: Methods and apparatuses for wafer support and release using sacrificial materials in wafer processing. In one embodiment, a solution of a sacrificial polymer is spray-coated on the wafer bump side to form a thin layer of the sacrificial polymer after solvent vaporization. An adhesive layer is then used to attach the wafer bump side onto a wafer support substrate over the sacrificial polymer to support the wafer in backside processing. After wafer thinning and backside metal deposition, the wafer is exposed to heat to thermally decompose the sacrificial polymer into gases. The decomposition of the sacrificial polymer reduces the adhesion of the adhesive layer to the bump side of the wafer such that, when the support substrate is detached from the wafer, the adhesive layer is detached together with the support substrate from the wafer bump side, leaving almost no residual traces.

Abstract: A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in a packaging material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.

Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Abstract: An apparatus comprising a substrate having a trench therein, the trench extending to an edge of the substrate, a waveguide array positioned in the trench, the waveguide array extending to the edge of the substrate, and a ferrule attached at or near the edge of the substrate and spanning a width of the waveguide array, the ferrule being directly in contact with a surface of the waveguide array. A process comprising positioning a waveguide in a trench on a substrate, the waveguide extending to an edge of the substrate, and attaching a ferrule at or near the edge of the substrate, the ferrule including a recess having a bottom, wherein the bottom is in direct contact with a surface of the waveguide.

Abstract: A system is disclosed. The system includes an external waveguide and an IC coupled to the external waveguide. The IC includes at least two lenses and a second waveguide. The lenses couple radiant energy from the external waveguide to the second waveguide.

Abstract: A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Abstract: Expanded bond pads are formed over a passivation layer on a semiconductor wafer before the wafer is diced into individual circuit chips. After dicing, the individual chips are packaged by fixing each chip within a package core and building up one or more metallization layers on the resulting assembly. In at least one embodiment, a high melting temperature (lead free) alternative bump metallurgy (ABM) form of controlled collapse chip connect (C4) processing is used to form relatively wide conducting platforms over the bond pads on the wafer.

Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: An electrooptic assembly including a microelectronic package and an optical substrate, wherein the optical substrate includes a coupler and a waveguide. An electrooptic element is disposed to convert an electrical signal from the microelectronic package to an optical signal for transmission to the coupler and waveguide, and/or to receive an optical signal and convert it to an electrical signal for transmission to the microelectronic package.

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

Abstract: An apparatus comprising a substrate having a trench therein, the trench extending to an edge of the substrate, a waveguide array positioned in the trench, the waveguide array extending to the edge of the substrate, and a ferrule attached at or near the edge of the substrate and spanning a width of the waveguide array, the ferrule being directly in contact with a surface of the waveguide array. A process comprising positioning a waveguide in a trench on a substrate, the waveguide extending to an edge of the substrate, and attaching a ferrule at or near the edge of the substrate, the ferrule including a recess having a bottom, wherein the bottom is in direct contact with a surface of the waveguide.