Abstract: A method, system, and computer program product in a logical partitioned data processing system are disclosed for providing a host bridge that implements extended error handling (EEH). If all devices coupled to the host bridge implement EEH, the host bridge is initialized to operate in EEH mode. In EEH mode, the devices handle any error that occurs within the devices without reporting the error to the host bridge. All partitions that share the host bridge continue to operate without being terminated while the devices are handling the error. If at least one device does not implement EEH, the host bridge is initialized to operate in non-EEH mode. In non-EEH mode, a machine check is generated by the host bridge when an error occurs within one of the devices resulting in the termination of all partitions that share the host bridge in response to a receipt of the machine check.

Abstract: Mechanisms for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Abstract: Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Abstract: In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Abstract: A system for reassigning root complex resources in a multi-root PCI express system identifies resources from a lower performing root complex port and reassigns those resources to the higher performing root complex. The system does not change the number of PCI Express lanes, the resources each root complex uses may be reassigned to allow those resources to be translated to available credits for an endpoint. For example, in one embodiment, two root complexes are configured as x8 root complexes with the root complex resources distributed across the two root complexes based upon the usage of the root complex resources.

Abstract: A system and method for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

Abstract: A system and method for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

Abstract: A method, system, and computer program product in a logical partitioned data processing system are disclosed for providing a host bridge that implements extended error handling (EEH). If all devices coupled to the host bridge implement EEH, the host bridge is initialized to operate in EEH mode. In EEH mode, the devices handle any error that occurs within the devices without reporting the error to the host bridge. All partitions that share the host bridge continue to operate without being terminated while the devices are handling the error. If at least one device does not implement EEH, the host bridge is initialized to operate in non-EEH mode. In non-EEH mode, a machine check is generated by the host bridge when an error occurs within one of the devices resulting in the termination of all partitions that share the host bridge in response to a receipt of the machine check.

Abstract: A method, system, and computer program product in a logical partitioned data processing system are disclosed for providing a host bridge that implements extended error handling (EEH). If all devices coupled to the host bridge implement EEH, the host bridge is initialized to operate in EEH mode. In EEH mode, the devices handle any error that occurs within the devices without reporting the error to the host bridge. All partitions that share the host bridge continue to operate without being terminated while the devices are handling the error. If at least one device does not implement EEH, the host bridge is initialized to operate in non-EEH mode. In non-EEH mode, a machine check is generated by the host bridge when an error occurs within one of the devices resulting in the termination of all partitions that share the host bridge in response to a receipt of the machine check.

Abstract: A method, system, and computer program product are disclosed for diagnosing and recovering from I/O subsystem errors. A data processing system includes a computer which includes a power subsystem and at least one I/O subsystem. A determination is made that an error occurred in the I/O subsystem. Registers in integrated circuits included within the I/O subsystem are accessed utilizing the power subsystem in order to diagnose the error while the I/O subsystem is in an error state.

Abstract: A method, system, and computer program product are disclosed for diagnosing and recovering from I/O subsystem errors. A data processing system includes a computer which includes a power subsystem and at least one I/O subsystem. A determination is made that an error occurred in the I/O subsystem. Registers in integrated circuits included within the I/O subsystem are accessed utilizing the power subsystem in order to diagnose the error while the I/O subsystem is in an error state.

Abstract: A method, system, and computer program product in a logical partitioned data processing system are disclosed for providing a host bridge that implements extended error handling (EEH). If all devices coupled to the host bridge implement EEH, the host bridge is initialized to operate in EEH mode. In EEH mode, the devices handle any error that occurs within the devices without reporting the error to the host bridge. All partitions that share the host bridge continue to operate without being terminated while the devices are handling the error. If at least one device does not implement EEH, the host bridge is initialized to operate in non-EEH mode. In non-EEH mode, a machine check is generated by the host bridge when an error occurs within one of the devices resulting in the termination of all partitions that share the host bridge in response to a receipt of the machine check.