Abstract: An engine monitor includes a first tuned modeling unit, a second tuned modeling unit and a monitoring unit. The first tuned modeling unit models dynamics of a first engine by processing first control data with a first engine model to provide modeled first engine parameter data, and at least partially adjusts the modeled first engine parameter data for model error in the first engine model to provide first tuned parameter data. The second tuned modeling unit models dynamics of a second engine by processing second control data with a second engine model to provide modeled second engine parameter data, and at least partially adjusts the modeled second engine parameter data for model error in the second engine model to provide second tuned parameter data. The monitoring unit correlates the first and the second tuned parameter data to monitor operation of the first and the second engines.

Abstract: A fault isolation method and system includes tailored fault isolators for each grouping of similar data to differentiate between one or several potential faults within any group.

Abstract: A fault isolation method and system includes tailored fault isolators for each grouping of similar data to differentiate between one or several potential faults within any group.

Abstract: A semiconductor memory device according to the invention includes a main memory comprising a number of memory sub-arrays, each coupled to an address and a data bus, for providing or receiving data to an intermediate interface unit. The intermediate interface unit provides data to and receives data from an output bus. Also included in the semiconductor memory device is redundancy circuit including a redundant memory coupled to the output bus for storing a subset of data from one of the sub-arrays in the event that the sub-array is defective. The redundancy circuit additionally includes address fuses for storing the sub-array addresses of the subset of data to be stored in the redundant storage, and compare circuitry coupled to the address bus for comparing the address bus to the stored array addresses to determine if there is a match.

Abstract: A package for a device having a sharp cutting edge, such as a bone saw, includes a tray having a bottom surface, a top surface and side walls. The side walls are connected between the bottom surface and the top surface. The top surface includes an upwardly facing central recessed portion for engaging a device such as a bone saw. The tray defines a downwardly facing recessed area adjacent the central portion. A protective strip of cushioning material is disposed within the downwardly facing recessed area and extends above and below the central portion. The protective strip prevents the device from engaging the side walls and is formed of a plastic sponge material which is soft, resilient and tear-resistant. A cover secured to the bottom surface of the tray retains the protective strip in operative position.

Abstract: A voltage level conversion buffer circuit including a first and a second transistor each having a gate, a drain, and a source. The drain of the first transistor and the gate of the second transistor are connected together to provide an input to the buffer circuit, and the gate of the first transistor and the drain of the second transistor are connected to a supply voltage. The sources of the first and second transistors are connected together to provide an output for the buffer circuit.