Abstract: A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

Abstract: To overcome these problems, the present invention generates two window strobes and uses the two window strobes to determine if skew between two signals meets predetermined criteria. One of the window strobes is used to test one of the signals, and the other window strobe is generated relative to the first window strobe. The second window strobe tests the other signal (or signals, if they are data signals). From the tests of the two window strobes, it can be determined if the skew between the first and second signals meets predetermined criteria. In particular, the two window strobes are placed relative to each other and to the signals being tested in such a way that when both window strobes indicate passing conditions, skew between the two signals is guaranteed.

Abstract: A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data.

Abstract: A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

Abstract: A fuse download system for programming decoders for redundancy. Auxiliary fuse banks have sets of fuses that store logic states that (a) select a redundant decoder and (b) indicate the address of a faulty row/column of memory cells. When the chip is first powered up, each set of fuses is accessed and downloaded to program selected redundant decoders. Because the fuse sets can be dynamically assigned to redundant decoders on an any-for-any basis, the fault tolerance of the redundancy system is enhanced.

Abstract: An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Abstract: A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available each of a plurality of sub-arrays of normal memory.

Abstract: An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.