Patents by Inventor Steven W. Wallace

Steven W. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6790753
    Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: September 14, 2004
    Assignee: Agere Systems Inc
    Inventors: John Charles Desko, Michael J Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R Jones, Thomas J. Krutsick, John Michael Siket, Jr., Brian Eric Thompson, Steven W. Wallace
  • Publication number: 20040089908
    Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Inventors: John Charles Desko, Michael J. Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R. Jones, Thomas J. Krutsick, John Michael Siket, Brian Eric Thompson, Steven W. Wallace
  • Patent number: 6690037
    Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 10, 2004
    Assignee: Agere Systems Inc.
    Inventors: John Charles Desko, Michael J Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R Jones, Thomas J. Krutsick, John Michael Siket, Jr., Brian Eric Thompson, Steven W. Wallace
  • Patent number: 5897362
    Abstract: The specification describes a gettering technique for bonded wafers. The handle wafer is provided with a phosphorus predeposition to getter impurities from the handle wafer. The surface to be bonded of the handle wafer is then polished to prepare the wafer for bonding. During polishing the top side phosphorus layer is removed, thereby eliminating the potential for updiffusion of phosphorus from the gettering layer into the device regions of the device layer. The phosphorus gettering layer on the backside of the handle wafer is retained for additional gettering during the bonding operation and during subsequent processing of the device wafer.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: April 27, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Steven W. Wallace