Abstract: An electrochemical sensor is provided that includes a housing having an outer wall, an axial bore circumscribed by the outer wall, and a barrier wall that aids in defining a reference cavity. The housing further including a plurality of cross members in spaced relation to one another disposed between the axial bore and the outer wall, each cross member defining an aperture. A junction plug is disposed at the distal end of the housing. The junction plug comprises a porous material that enables ionic flow through the junction plug. The sensor enables ionic communication between the target fluid and the reference electrode within the reference cavity through the apertures of the plurality of cross members. In this manner, the sensor provides generally a long, tortuous flow path, or salt bridge, between the target fluid and the reference electrode, resulting in a high resistance factor for the sensor.

Abstract: An electrochemical sensor is provided that includes a housing defining a cavity for a reference electrolyte and defining an opening to the cavity configured to be proximate to a target fluid. The sensor further includes a junction plug comprising a porous material and a cross member impermeable to a target fluid positioned between the junction plug and the cavity. The cross member includes a planar portion disposed against the junction plug that defines an aperture to enable electrochemical communication between the target fluid and the reference electrolyte.

Abstract: An electrochemical sensor is provided that includes a housing having an outer wall, a plurality of longitudinal walls disposed within the outer wall, and a reference chamber housing a reference electrode. The longitudinal walls define a plurality of longitudinal chambers. Ionic communication between the target fluid and the reference electrode passes sequentially through each of longitudinal chambers from a first longitudinal chamber to the reference chamber. In this manner, the sensor provides generally a long, tortuous flow path, or salt bridge, between the target fluid and the reference electrode, resulting in a high resistance factor for the sensor.

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

Abstract: A method of reducing discordance among components of a molded trim piece assembly includes making each of the plurality of components according to a component configuration pattern adapted to mitigate deformation of the plurality of components, and making each of the plurality of components according to a joint configuration pattern adapted to mitigate misalignment between the plurality of components at a joint. A machine includes a molded trim piece assembly configured to amount to a body of the machine, such as to a fender of the machine, which includes a plurality of components having a component configuration pattern adapted to mitigate deformation of the plurality of components and a joint configuration pattern adapted to mitigate misalignment at a joint between the plurality of components, when mounted to the body.

Abstract: An electrochemical sensor is provided that includes a housing having an outer wall, a plurality of longitudinal walls disposed within the outer wall, and a reference chamber housing a reference electrode. The longitudinal walls define a plurality of longitudinal chambers. Ionic communication between the target fluid and the reference electrode passes sequentially through each of longitudinal chambers from a first longitudinal chamber to the reference chamber. In this manner, the sensor provides generally a long, tortuous flow path, or salt bridge, between the target fluid and the reference electrode, resulting in a high resistance factor for the sensor.

Abstract: An electrochemical sensor is provided that includes a housing having an outer wall, an axial bore circumscribed by the outer wall, and a barrier wall that aids in defining a reference cavity. The housing further including a plurality of cross members in spaced relation to one another disposed between the axial bore and the outer wall, each cross member defining an aperture. A junction plug is disposed at the distal end of the housing. The junction plug comprises a porous material that enables ionic flow through the junction plug. The sensor enables ionic communication between the target fluid and the reference electrode within the reference cavity through the apertures of the plurality of cross members. In this manner, the sensor provides generally a long, tortuous flow path, or salt bridge, between the target fluid and the reference electrode, resulting in a high resistance factor for the sensor.

Abstract: An electrochemical sensor is provided that includes a housing defining a cavity for a reference electrolyte and defining an opening to the cavity configured to be proximate to a target fluid. The sensor further includes a junction plug comprising a porous material and a cross member impermeable to a target fluid positioned between the junction plug and the cavity. The cross member includes a planar portion disposed against the junction plug that defines an aperture to enable electrochemical communication between the target fluid and the reference electrolyte.

Abstract: A method for fabricating an induction motor rotor lamination includes using an indexed notching die to punch a plurality of closed rotor slots at different distances from a center point of rotation by punching a first rotor slot, changing the position of a center point of the rotor lamination with respect to the notching die, and punching a second rotor slot. In another embodiment, a plurality of rotor slit patterns are punched using a variable depth indexed notching die including at least two rotor slit punching portions, one being deeper than another, by punching a first rotor slit pattern, changing the depth of closure of the notching die, and punching a second rotor slit pattern with the second rotor slit pattern having a different number of rotor slits than the first.

Abstract: A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.

Abstract: A method for fabricating an induction motor rotor lamination includes using an indexed notching die to punch a plurality of closed rotor slots at different distances from a center point of rotation by punching a first rotor slot, changing the position of a center point of the rotor lamination with respect to the notching die, and punching a second rotor slot. In another embodiment, a plurality of rotor slit patterns are punched using a variable depth indexed notching die including at least two rotor slit punching portions, one being deeper than another, by punching a first rotor slit pattern, changing the depth of closure of the notching die, and punching a second rotor slit pattern with the second rotor slit pattern having a different number of rotor slits than the first.

Abstract: A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and applying a controllable delay at each of the local clock buffers in response to a phase comparison of clock signals from one or more adjacent clock zones. The system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and localized phase comparators. By adjusting each localized clock buffer delay unit in response to measured clock signal phase differences from adjacent circuit zones, clock skew problems can be minimized across various clock zones on a VLSI circuit.

Abstract: A method for fabricating an induction motor rotor lamination includes using an indexed notching die to punch a plurality of closed rotor slots at different distances from a center point of rotation by punching a first rotor slot, changing the position of a center point of the rotor lamination with respect to the notching die, and punching a second rotor slot. In another embodiment, a plurality of rotor slit patterns are punched using a variable depth indexed notching die including at least two rotor slit punching portions, one being deeper than another, by punching a first rotor slit pattern, changing the depth of closure of the notching die, and punching a second rotor slit pattern with the second rotor slit pattern having a different number of rotor slits than the first.

Abstract: A file system created in a flash EEPROM memory array for an embedded system having a plurality of blocks of flash memory cells, each block being divided into identical-sized areas capable of being addressed, the file system including a data structure positioned at a predetermined one of the areas on each block of a flash EEPROM memory array, the data structure storing a logical identification of data stored in each of the areas, the logical identifications of data being stored sequentially in the physical order of the areas on the block, a controller implemented process for searching the predetermined ones of the areas on each block to detect a logical identification of data, and means for accessing the physical area associated with any logical identification of data which is detected.

Abstract: A solid state memory disk that stores data on a sector basis is described. The solid state disk includes an array of FLASH memory devices, which store the sectors of data. Each block of memory within the FLASH array includes data space for storing many sectors of data and a block sector translation table. The block sector translation table identifies each sector of data stored in the block's data space by a sector number. The solid state disk also includes a controller. Among its many responsibilities, the controller manages the writing of sector data into the array and the reading of sectors of data from the array. The controller responds to a write request by seeking an earlier version of the sector which has a logical sector number equal to the sector's sector number and marking that sector dirty. Afterward, the controller allocates free memory space for the sector of data. The sector of data is then written into the allocated memory space.

Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Abstract: A method of cleaning-up a solid state memory disk is described. Clean-up begins with the selection of a focus block for clean-up. Next, on a sector-by-sector basis, memory is allocated within a destination block to store valid sectors of user data. User data is then copied into the destination block on a sector-by-sector basis. Afterward, the focus block is erased, converting dirty sectors into free memory without loss of valid sectors of data.

Abstract: A solid state memory disk with increased reserve memory is described. The solid state memory disk includes an array of solid state memory devices for storing user data and reserve memory, which includes both free memory and dirty memory. The solid state memory disk also includes a controller, a clean-up state machine, and a data compressor. The data compressor increases reserve memory by compressing data received from a host and coupling compressed data to the array of memory devices under the control of the controller. In response to write commands from the host, the controller writes a first sector data, which has been compressed, to a first location in a first block within a memory device. Reserve memory within the array is thus increased, so long as the maximum number of sectors the host is allowed to write is less the average compression ratio of the data compressor multiplied by the capacity of the solid state disk. A method of increasing reserve memory in a solid state disk is also described.

Abstract: Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

Abstract: A method of allocating free physical memory in a solid state memory disk for a sector of data of a given size is described. Allocation begins by determining whether sufficient free memory remains in the block to which the previous sector of data was written. If there is not sufficient free memory remaining, then selection of another block to allocate the sector of data begins. The selection is based on the sum of the amount of free memory in a selected block and one of the following: 1) the amount of invalid data in the block; 2) the cycle count for the block; 3) the amount of invalid data as compared to a maximum amount of invalid data for all non-volatile memory devices associated with the block; and 4) the number of blocks already allocated to all non-volatile memory devices associated with the block. Afterward, the block with the greatest amount of available memory is selected to store the sector of data.