Patents by Inventor Steven William Tomashot

Steven William Tomashot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6438062
    Abstract: An improved and much simplified method to access data banks in a memory system which provides the option of opening more than one bank in a single command. This is especially useful to achieve bursts of data across bank boundaries in a memory system of synchronous dynamic random access memory cards having fast memory bus speeds. The method decodes signals to generate a single command which may open one or more memory bank at a time. Logic can increment the banks, decrement a bank counter, and, if necessary, increment/decrement a row and/or uniquely address a column so that continual data bursts can be achieved seamlessly across bank boundaries in synchronous dynamic random access memory systems. The data banks may be opened all at once, or can be opened sequentially in a staggered manner according to a synchronous or asynchronous, with respect to the memory clock, time delay During that time delay a nop command or a chip deselect command may execute.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: August 20, 2002
    Assignee: International Business Machines Corporation
    Inventors: Michael William Curtis, William Paul Hovis, Steven William Tomashot
  • Patent number: 6434082
    Abstract: A clocked memory device includes a programming mechanism that allows the write recovery time during a command with auto precharge enabled to be dynamically set to some function of the input clock. In the preferred embodiments, the programming mechanism includes a control register with programmable bits that allows specifying the write recovery time according to the bit values written to the control register. For example, write recovery time could be specified as a whole or fractional number of clock cycles. By specifying the write recovery time as a function of the clock that may be dynamically set, the clocked memory device may be used at its highest performance capabilities over a wide range of operating frequencies.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: William Paul Hovis, Steven William Tomashot
  • Patent number: 6243283
    Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: June 5, 2001
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, John A. Fifield, Erik Leigh Hedberg, Russell J. Houghton, Timothy Dooling Sullivan, Steven William Tomashot, William Robert Tonti
  • Patent number: 6141245
    Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, John A. Fifield, Erik Leigh Hedberg, Russell J. Houghton, Timothy Dooling Sullivan, Steven William Tomashot, William Robert Tonti
  • Patent number: 5901093
    Abstract: An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: May 4, 1999
    Assignee: International Business Machines Corporation
    Inventors: Nathan Rafael Hiltebeitel, Robert Tamlyn, Steven William Tomashot, Thomas Walter Wyckoff
  • Patent number: 5787457
    Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column select means for selecting a desired column of the row of data. A randomly addressable row register stores a row of data latched by the sense amplifiers. A select logic gating means, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed. Data to be input into the cached SDRAM during a Write operation is received by the sense amplifiers and written into the memory bank array.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: July 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Christopher Paul Miller, Jim Lewis Rogers, Steven William Tomashot
  • Patent number: 5745431
    Abstract: An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the address input signals input to the address decode circuit with the control signal.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: April 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Dale Edward Pontius, Steven William Tomashot, Toshiaki Kirihata, Robert Henry Kruggel