Abstract: A communication device is disclosed. The device may be in particular a radio transmitter and a receiver that can operate with low power consumption and with improved interference rejection, therefore particularly suitable for use in low-power communication systems, such as wireless sensor networks and wireless body area networks. In one aspect, multiple frequency tones (carriers) are used to carry information from the transmitter, such that a RF signal having multiple radio frequency components is produced and transmitted. In the receiver, an envelope detector is still the RF down-converter. After down-converting intermodulation components are extracted containing amplitude, phase and frequency information of the multiple radio frequency components. This allows the desired signal (the baseband information) to be distinguished from the carriers and unwanted interference.

Abstract: The application describes methods and apparatus for chemical sensing, e.g. gas sensing, which have high sensitivity but low power operation. A sensor is described having a flexible membrane comprising a III/N heterojunction structure configured so as to form a two dimensional electron gas within said structure. A sensing material is disposed on at least part of the flexible membrane, the sensing material being sensitive to one or more target chemicals so as to undergo a change in physical properties in the presence of said one or more target chemicals. The sensing material is coupled to said heterojunction structure such that said change in physical properties of the sensing material imparts a change in stress within the heterojunction structure which modulates the resistivity of the two dimensional electron gas.

Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.