Patents by Inventor Stuart Haug

Stuart Haug has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10516421
    Abstract: Embodiments in accordance with the present disclosure are directed to communications apparatuses and methods thereof that includes a radio frequency (RF) front-end circuitry and RF back-end circuitry. The RF front-end circuit receives sets of RF signals concurrently and as transmitted from at least two disparate communication networks. The front-end circuitry includes a tunable radio having at least one antenna feeding signal conditioning and down conversion circuitry, and decimation circuitry. The decimation circuitry filters and decimates data associated with the RF signals into a plurality of digital data streams. The RF back-end circuitry includes a plurality of digital-signal processors (DSPs) that extract raw data packets from the digital data streams and a microprocessor. The microprocessor transmits the plurality of digital data streams to the plurality of DSPs and transmits the extracted raw data packets, received from the plurality of DSPs, to an end-user device.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 24, 2019
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Patent number: 10270491
    Abstract: Power-line communication (PLC) systems collect information over power lines from end-point devices respectively associated with customer sites, for assessment by a central processing circuit operated on behalf of a power utility company. In the PLC system, each of a number of PLC data-collector circuits includes a plurality of data interface units and PLC end-point device data computation circuit. Typically, one data interface circuit is located proximate, and another is distal, the location of the computation circuit. Each data interface unit includes a transformer circuit for selectively receiving data from a subset of the end-point devices via the power lines, a transformer-coupling circuit for selectively sending data to the subset of the end-point devices via the power lines, and a high-throughput data driver circuit for outputting data in accordance with a data-transfer protocol which is common to the other high throughput driver circuits which operate in accordance with the data-transfer protocol.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 23, 2019
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Stuart Haug, Damian Bonicatto, Rolf Flen, Robert Zeppetelle
  • Patent number: 10250294
    Abstract: In one or more embodiments, a plurality of PLC endpoints and a data processing circuit are configured to share information, in the form of data blocks over power lines in a power line communication (PLC) network. A first signal representing a transmitted one of the data blocks is received over a first one of the plurality of different communication channels. A second signal representing the transmitted one of the data blocks is received over a second one of the plurality of different communication channels. Information carried by said one of the data blocks is discerned, as a function of a signal versus noise measure associated with the first signal and the second signal, by combining energy from the first and second signals, and converting the combined energy for generating output data.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: April 2, 2019
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Stuart Haug, Damian Bonicatto
  • Publication number: 20190068243
    Abstract: Power-line communication (PLC) systems collect information over power lines from end-point devices respectively associated with customer sites, for assessment by a central processing circuit operated on behalf of a power utility company. In the PLC system, each of a number of PLC data-collector circuits includes a plurality of data interface units and PLC end-point device data computation circuit. Typically, one data interface circuit is located proximate, and another is distal, the location of the computation circuit. Each data interface unit includes a transformer circuit for selectively receiving data from a subset of the end-point devices via the power lines, a transformer-coupling circuit for selectively sending data to the subset of the end-point devices via the power lines, and a high-throughput data driver circuit for outputting data in accordance with a data-transfer protocol which is common to the other high throughput driver circuits which operate in accordance with the data-transfer protocol.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Stuart Haug, Damian Bonicatto, Rolf Flen, Robert Zeppetelle
  • Publication number: 20170163310
    Abstract: In one or more embodiments, a plurality of PLC endpoints and a data processing circuit are configured to share information, in the form of data blocks over power lines in a power line communication (PLC) network. A first signal representing a transmitted one of the data blocks is received over a first one of the plurality of different communication channels. A second signal representing the transmitted one of the data blocks is received over a second one of the plurality of different communication channels. Information carried by said one of the data blocks is discerned, as a function of a signal versus noise measure associated with the first signal and the second signal, by combining energy from the first and second signals, and converting the combined energy for generating output data.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 8, 2017
    Inventors: Stuart Haug, Damian Bonicatto
  • Patent number: 9525462
    Abstract: In one or more embodiments, a plurality of PLC endpoints and a data processing circuit are configured to share information, in the form of data blocks over power lines in a power line communication (PLC) network. A first signal representing a transmitted one of the data blocks is received over a first one of the plurality of different communication channels. A second signal representing the transmitted one of the data blocks is received over a second one of the plurality of different communication channels. Information carried by said one of the data blocks is discerned, as a function of a signal versus noise measure associated with the first signal and the second signal, by aligning phases of the first and second signals, combining energy from the first and second signals as aligned, and converting the combined energy and therefrom providing output data representing the transmitted one of the data blocks.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 20, 2016
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Stuart Haug, Damian Bonicatto
  • Patent number: 8731076
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically selecting symbol periods for communications signals and recovering symbols from the communications signals. In one aspect, a method includes receiving a plurality of communications signals over a plurality of different communications channels and determining symbol period end times for the communications signals. A determination is made that a present time is coincident with an end of a sample period for the communications signals and that an end of the symbol period for the communications signals received over at least one of the communications channels is coincident with the present time. In turn, data are provided that represent a symbol received over each communications channel for which an end of the symbol period is coincident with the present time.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: May 20, 2014
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Patent number: 8681619
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for transmitting data. In one aspect, a method obtains a baseline data rate for transmissions from a node that are received over a channel of a power line communications system and a set of available modulation techniques for the node. The set of available modulation techniques can include at least two modulation techniques with which the node is configured to encode data that are transmitted over the channel. Using the set of available modulation techniques, a modulation technique that is capable of providing at least the baseline data rate with at least a threshold confidence for the node is selected. In turn, data is provided to the node specifying the selected modulation technique.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: March 25, 2014
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Patent number: 8625719
    Abstract: Disclosed are various embodiments for dividing workload in a digital signal processing system. In one embodiment, the system includes at least one analog-to-digital converter configured to receive a three phase analog waveform and a digital waveform. The system can also include a first DSP configured to interface with an external computer and a second DSP configured to receive the digital waveform and isolate a specified frequency range. The system can also include a plurality of DSP's configured to extract specified channels from the specified frequency range and output the extracted channel data.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: January 7, 2014
    Assignee: Landis+Gyr Technologies, LLC
    Inventors: Stuart Haug, Chad Wolter, Damian Bonicatto, Verne Olson, Robert Zeppetelle
  • Publication number: 20120106664
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically selecting symbol periods for communications signals and recovering symbols from the communications signals. In one aspect, a method includes receiving a plurality of communications signals over a plurality of different communications channels and determining symbol period end times for the communications signals. A determination is made that a present time is coincident with an end of a sample period for the communications signals and that an end of the symbol period for the communications signals received over at least one of the communications channels is coincident with the present time. In turn, data are provided that represent a symbol received over each communications channel for which an end of the symbol period is coincident with the present time.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 3, 2012
    Applicant: HUNT TECHNOLOGIES, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Patent number: 8144816
    Abstract: Disclosed are various embodiments of a programmable slicer in a digital signal processing system and/or software radio system. In one embodiment, a plurality of demodulation schemes and a plurality of channel definitions are stored in a channel allocation table. An analog waveform is received and converted into at least one digital waveform. A specified frequency range is isolated from the at least one digital waveform. The magnitude of tones within the specified frequency range is measured and stored in a signal magnitude table. Symbols and/or bits are decoded from the signal magnitude table by applying a demodulation schemes and channel definitions to the magnitudes stored in the signal magnitude table.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: March 27, 2012
    Assignee: Hunt Technologies, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Publication number: 20110249678
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for transmitting data. In one aspect, a method obtains a baseline data rate for transmissions from a node that are received over a channel of a power line communications system and a set of available modulation techniques for the node. The set of available modulation techniques can include at least two modulation techniques with which the node is configured to encode data that are transmitted over the channel. Using the set of available modulation techniques, a modulation technique that is capable of providing at least the baseline data rate with at least a threshold confidence for the node is selected. In turn, data is provided to the node specifying the selected modulation technique.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Applicant: HUNT TECHNOLOGIES, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Patent number: 7774530
    Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 10, 2010
    Assignee: Hunt Technologies, LLC
    Inventors: Stuart Haug, Chad Wolter, Damian Bonicatto, Verne Olson, Robert Zeppetelle, Matt Tilstra
  • Publication number: 20090110121
    Abstract: Disclosed are various embodiments of a programmable slicer in a digital signal processing system and/or software radio system. In one embodiment, a plurality of demodulation schemes and a plurality of channel definitions are stored in a channel allocation table. An analog waveform is received and converted into at least one digital waveform. A specified frequency range is isolated from the at least one digital waveform. The magnitude of tones within the specified frequency range is measured and stored in a signal magnitude table. Symbols and/or bits are decoded from the signal magnitude table by applying a demodulation schemes and channel definitions to the magnitudes stored in the signal magnitude table.
    Type: Application
    Filed: October 27, 2008
    Publication date: April 30, 2009
    Applicant: HUNT TECHNOLOGIES, LLC
    Inventors: Damian Bonicatto, Stuart Haug
  • Publication number: 20080304595
    Abstract: Disclosed are various embodiments for dividing workload in a digital signal processing system. In one embodiment, the system includes at least one analog-to-digital converter configured to receive a three phase analog waveform and a digital waveform. The system can also include a first DSP configured to interface with an external computer and a second DSP configured to receive the digital waveform and isolate a specified frequency range. The system can also include a plurality of DSP's configured to extract specified channels from the specified frequency range and output the extracted channel data.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 11, 2008
    Applicant: Hunt Technologies, LLC
    Inventors: Stuart Haug, Chad Wolter, Damian Bonicatto, Verne Olson, Robert Zeppetelle
  • Publication number: 20080307136
    Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 11, 2008
    Applicant: HUNT TECHNOLOGIES, LLC
    Inventors: Stuart Haug, Chad Wolter, Damian Bonicatto, Verne Olson, Robert Zeppetelle, Matt Tilstra
  • Publication number: 20070018850
    Abstract: An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.
    Type: Application
    Filed: September 26, 2006
    Publication date: January 25, 2007
    Applicant: Hunt Technologies, Inc.
    Inventors: Rolf Flen, Stuart Haug, Matthew Ruohoniemi
  • Publication number: 20050055586
    Abstract: An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.
    Type: Application
    Filed: July 24, 2003
    Publication date: March 10, 2005
    Applicant: Hunt Technologies, Inc.
    Inventors: Rolf Flen, Stuart Haug, Matthew Ruohoniemi
  • Publication number: 20050017848
    Abstract: An endpoint is configured for communication with a distribution substation. The endpoint includes a receiver conditioning block and a receiver processing block. The receiver conditioning block is positioned downstream from the distribution substation, and arranged to provide an analog signal that is responsive to the power signal from the distribution line. The receiver processing block is configured to extract encoded data from the power signal by under-sampling the analog signal, and processing the under-sampled analog signal such that fundamental and harmonic frequencies associated with the power signal are suppressed. Command signals from the distribution substation are extracted from the power-line. Each endpoint is addressable by an ID code, and is configurable via downstream command signals that are associated with the ID code. The endpoint collects data at demand based and schedule based intervals.
    Type: Application
    Filed: July 24, 2003
    Publication date: January 27, 2005
    Applicant: Hunt Technologies, Inc.
    Inventors: Rolf Flen, Stuart Haug, Matthew Ruohoniemi
  • Publication number: 20050017849
    Abstract: An endpoint in a power distribution system includes a transmitter. The transmitter includes a transformer, a half-bridge driver, a first and second driver, and a resonant circuit. A primary winding from the transformer is coupled to a power distribution line, while the secondary winding is coupled to the transmitter. The half-bridge drive circuit selectively asserts drive signals. The resonant circuit has a natural resonant frequency in an audio frequency range. The half-bridge driver is arranged to selectively activate the first and second drivers such that the power-line is modulated with a square-wave signal at a frequency that is associated with encoded data. The half-bridge driver circuit can also be arranged to provide power to the transmitter, and to the endpoint.
    Type: Application
    Filed: July 24, 2003
    Publication date: January 27, 2005
    Applicant: Hunt Technologies, Inc.
    Inventors: Rolf Flen, Stuart Haug, Matthew Ruohoniemi