Abstract: An apparatus and method are disclosed for buffering graphics commands in a video graphics system, and for implementing graphics macro commands. The invention makes use of off-screen portions of video memory to create a dynamic command FIFO for commands, and to store command sequences for later or repeated use ("macros"). A command FIFO controller is provided, along with an on-chip bus FIFO and an on-chip command buffer (which is also a FIFO). Several multiplexers are also provided, so as to enable the command FIFO controller to create several different paths for commands coming into the graphics controller. Incoming commands may be routed to the command execution circuitry in several different ways: through the bus FIFO and command buffer to the command execution circuitry, directly to the command execution circuitry by bypassing the bus FIFO and command buffer, or from the bus FIFO into video memory to be stored in a dynamic command FIFO and later retrieved and sent into the command buffer.

Abstract: A video controller has one or more shared pins coupled to respective configuration signals. The shared pins are also coupled to other devices external to the video controller. Responsive to a reset signal, the configuration signals are stored in a configuration register. At other times, the external devices can overcome the configuration signals such that the shared pins may be used for other operations of the video subsystem.