Abstract: A prototype system is described having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract: An interconnection system (110) interconnects a plurality of reusable functional units (105a), (105b), (105c). The system (110) comprises a plurality of nodes (135), (140), (145), (150), (155), (160) each node communicating with a functional unit. A plurality of data packets are transported between the functional units. Each data packet has routing information associated therewith to enable a node to direct the data packet via the interconnection system.