Patents by Inventor Stuart Spitzer
Stuart Spitzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8274073Abstract: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the passive layer and the second electrode. In undertaking an operation on the memory device, ions moves into within and from within the active layer, and the active layer is oriented so that the atoms of the active layer provide minimum obstruction to the movement of the ions into, within and from the active layer.Type: GrantFiled: March 11, 2005Date of Patent: September 25, 2012Assignee: Spansion LLCInventors: Juri Krieger, Stuart Spitzer
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Patent number: 7981773Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: May 22, 2009Date of Patent: July 19, 2011Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Publication number: 20090233422Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: SPANSION LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7550761Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: December 26, 2006Date of Patent: June 23, 2009Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7450416Abstract: The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so determined threshold voltage of the memory-diode.Type: GrantFiled: December 23, 2004Date of Patent: November 11, 2008Assignee: Spansion LLCInventors: Swaroop Kaza, Juri Krieger, David Gaun, Stuart Spitzer, Richard Kingsborough, Zhida Lan, Colin S. Bill, Wei Daisy Cai, Igor Sokolik
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Patent number: 7378682Abstract: The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for receiving a charged specie from the passive layer. The active layer is a mixture of (i) a first polymer, and (ii) a second polymer for enhancing ion transport, improving the interface and promoting a rapid and substantially uniform distribution of the charged specie in the active layer, i.e., preventing a localized injection of the charged species. These features result in a memory element with improved stability, a more controllable ON-state resistance, improved switching speed and a lower programming voltage.Type: GrantFiled: February 7, 2005Date of Patent: May 27, 2008Assignee: Spanson LLCInventors: David Gaun, Swaroop Kaza, Stuart Spitzer, Juri Krieger, Richard Kingsborough
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Patent number: 7379317Abstract: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.Type: GrantFiled: December 23, 2004Date of Patent: May 27, 2008Assignee: Spansion LLCInventors: Colin S. Bill, Swaroop Kaza, Tzu-Ning Fang, Stuart Spitzer
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Patent number: 7344913Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an active layer and passive layer. The active layer is formed using spin on techniques and contains an organic semiconductor doped with a metal salt.Type: GrantFiled: April 6, 2005Date of Patent: March 18, 2008Assignee: Spansion LLCInventors: Richard P. Kingsborough, William Leonard, Igor Sokolik, Stuart Spitzer, Zhida Lan
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Patent number: 7307338Abstract: Systems and methodologies are provided for forming three dimensional memory structures that are fabricated from blocks of individual polymer memory cells stacked on top of each other. Such a polymer memory structure can be formed on top of control component circuitries employed for programming a plurality of memory cells that form the stacked three dimensional structure. Such an arrangement provides for an efficient placement of polymer memory cell on a wafer surface, and increases amount of die space available for circuit design.Type: GrantFiled: July 26, 2004Date of Patent: December 11, 2007Assignee: Spansion LLCInventors: Aaron Mandell, Juri H Krieger, Igor Sokolik, Richard P Kingsborough, Stuart Spitzer
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Patent number: 7289353Abstract: Systems and methodologies are provided for adjusting threshold associated with a polymer memory cell's operation by applying thereupon a regulated electric field and/or voltage pulse width, during a post fabrication stage. Such customization of programming thresholds can typically be obtained at any cycle of programming the memory cell, to increase flexibility in circuit design. Accordingly, the present invention supplies both a current-voltage domain, and/or a frequency-time domain, to facilitate adjusting the program thresholds of the polymer memory cell.Type: GrantFiled: August 17, 2004Date of Patent: October 30, 2007Assignee: Spansion, LLCInventors: Stuart Spitzer, Juri H Krieger, David Gaun
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Patent number: 7269050Abstract: The present invention is a method of programming a memory device, wherein different levels or magnitudes of current may be applied to and imposed on the memory device so that any one of a plurality of memory states may be realized. A read step indicates the so determined state of the memory device.Type: GrantFiled: June 7, 2005Date of Patent: September 11, 2007Assignee: Spansion LLCInventors: Swaroop Kaza, David Gaun, Stuart Spitzer, Juri Krieger
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Patent number: 7221599Abstract: Systems and methodologies are provided for activating a polymer memory cell(s) after production by subjecting the polymer memory cell to an electrical field, for an initialization thereof. Such initialization can facilitate the distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell. The memory cell can include various layers of alternating passive and active media, which are sandwiched between conducting electrode layers.Type: GrantFiled: November 1, 2004Date of Patent: May 22, 2007Assignee: Spansion, LLCInventors: David Gaun, Juri H Krieger, Stuart Spitzer
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Publication number: 20070102743Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: ApplicationFiled: December 26, 2006Publication date: May 10, 2007Applicant: SPANSION LLCInventors: Juri Krieger, Stuart Spitzer
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Patent number: 7199394Abstract: Systems and methodologies are provided for of enabling a polymer memory cell to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell. Short retention times can be obtained by programming the polymer memory cell via a low current or a low electrical field. Similarly, long retention times can be obtained by employing a high current or electrical field to program the polymer memory cell.Type: GrantFiled: August 17, 2004Date of Patent: April 3, 2007Assignee: Spansion LLCInventors: Aaron Mandell, Michael A VanBuskirk, Stuart Spitzer, Juri H Krieger
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Publication number: 20070007585Abstract: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes and an active layer between the first and second electrodes, the active layer being of a material containing randomly oriented pores which are interconnected to form passages through the active layer.Type: ApplicationFiled: July 5, 2005Publication date: January 11, 2007Inventors: Igor Sokolik, Richard Kingsborough, David Gaun, Swaroop Kaza, Stuart Spitzer, Suzette Pangrle
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Patent number: 7157732Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: July 1, 2004Date of Patent: January 2, 2007Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7154769Abstract: The present memory device includes a first electrode, a passive layer on and in contact with the first electrode, the passive layer including copper sulfide, a barrier layer on and in contact with the passive layer, an active layer on and in contact with the barrier layer, and a second electrode on and in contact with the active layer. The inclusion of the barrier layer in this environment increases switching speed of the memory device, while also improving data retention thereof.Type: GrantFiled: February 7, 2005Date of Patent: December 26, 2006Assignee: Spansion LLCInventors: Juri Krieger, Stuart Spitzer
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Publication number: 20060274567Abstract: The present invention is a method of programming a memory device, wherein different levels or magnitudes of current may be applied to and imposed on the memory device so that any one of a plurality of memory states may be realized. A read step indicates the so determined state of the memory device.Type: ApplicationFiled: June 7, 2005Publication date: December 7, 2006Inventors: Swaroop Kaza, David Gaun, Stuart Spitzer, Juri Krieger
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Publication number: 20060245235Abstract: Systems and methodologies are provided for forming a diode component operative (e.g., connected in series) with active and passive layer of a resistance switching memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a memory cell having a passive and active layer. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of the array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: ApplicationFiled: May 2, 2005Publication date: November 2, 2006Inventors: Juri Krieger, Stuart Spitzer
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Patent number: 7122853Abstract: Systems and methodologies are provided for simplifying a polymer memory cell's operation by employing a post polymer growth treatment to form ionic or super ionic metal compounds therein. Such post polymer growth treatment facilitates distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell, and mitigates (or eliminates) a need for initialization procedures. Moreover, the post treatment of the present invention can also facilitate controlling a distribution of various thresholds (e.g., write and erase threshold), and set them to predetermined values Accordingly, variability in threshold values of polymer memory cells that can result from initialization processes can be mitigated (or eliminated), and thicker polymer layers can be employed without an initialization penalty.Type: GrantFiled: August 17, 2004Date of Patent: October 17, 2006Assignee: FASL, Inc.Inventors: David Gaun, Stuart Spitzer, Nicolay F Yudanov