Patents by Inventor Stuart Zachary Jacobs
Stuart Zachary Jacobs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11662934Abstract: A data processing system includes a system fabric, a system memory, a memory controller, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link to a destination host with which the source host is non-coherent. A plurality of processing units is configured to execute a logical partition and to migrate the logical partition to the destination host via the communication link. Migration of the logical partition includes migrating, via a communication link, the dataset of the logical partition executing on the source host from the system memory of the source host to a system memory of the destination host. After migrating at least a portion of the dataset, a state of the logical partition is migrated, via the communication link, from the source host to the destination host, such that the logical partition thereafter executes on the destination host.Type: GrantFiled: December 15, 2020Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Steven Leonard Roberts, David A. Larson Stanton, Peter J. Heyrman, Stuart Zachary Jacobs, Christian Pinto
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Publication number: 20220188007Abstract: A data processing system includes a system fabric, a system memory, a memory controller, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link to a destination host with which the source host is non-coherent. A plurality of processing units is configured to execute a logical partition and to migrate the logical partition to the destination host via the communication link. Migration of the logical partition includes migrating, via a communication link, the dataset of the logical partition executing on the source host from the system memory of the source host to a system memory of the destination host. After migrating at least a portion of the dataset, a state of the logical partition is migrated, via the communication link, from the source host to the destination host, such that the logical partition thereafter executes on the destination host.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Inventors: Steven Leonard Roberts, David A. Larson Stanton, Peter J. Heyrman, Stuart Zachary Jacobs, Christian Pinto
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Patent number: 11281483Abstract: Within a hashed page table maintained by a hypervisor, a special host real address configured to access a hardware device using access data intended to be invalidated is identified as part of a firmware assisted dump process for a virtual machine executing on the hypervisor. The special host real address is translated to a corresponding special guest real address. Within the hashed page table, the special host real address is replaced with the corresponding special guest real address, and the corresponding special guest real address is marked as invalid and requiring special handling. Subsequent to the replacing, the special host real address is invalidated. The special guest real address and translated address information are provided to the virtual machine subsequent to the invalidating, the translated address information comprising a set of host real addresses translated to corresponding guest real addresses.Type: GrantFiled: October 16, 2019Date of Patent: March 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Brian Wallis, Wade Byron Ouren, Stuart Zachary Jacobs, Troy David Armstrong, Kenneth Charles Vossen
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Patent number: 11249804Abstract: A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.Type: GrantFiled: October 7, 2019Date of Patent: February 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Anthony Larson Stanton, Stuart Zachary Jacobs, Troy David Armstrong, Peter J. Heyrman
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Publication number: 20210117215Abstract: Within a hashed page table maintained by a hypervisor, a special host real address configured to access a hardware device using access data intended to be invalidated is identified as part of a firmware assisted dump process for a virtual machine executing on the hypervisor. The special host real address is translated to a corresponding special guest real address. Within the hashed page table, the special host real address is replaced with the corresponding special guest real address, and the corresponding special guest real address is marked as invalid and requiring special handling. Subsequent to the replacing, the special host real address is invalidated. The special guest real address and translated address information are provided to the virtual machine subsequent to the invalidating, the translated address information comprising a set of host real addresses translated to corresponding guest real addresses.Type: ApplicationFiled: October 16, 2019Publication date: April 22, 2021Applicant: International Business Machines CorporationInventors: Christopher Brian Wallis, Wade Byron Ouren, Stuart Zachary Jacobs, Troy David Armstrong, Kenneth Charles Vossen
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Publication number: 20210103474Abstract: A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.Type: ApplicationFiled: October 7, 2019Publication date: April 8, 2021Applicant: International Business Machines CorporationInventors: David Anthony Larson Stanton, Stuart Zachary Jacobs, Troy David Armstrong, Peter J. Heyrman
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Patent number: 8140822Abstract: Maintaining data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target computer system. A first page table stores a plurality of page entries made within a logically partitioned environment. A second page table stores one or more page entries generated during the migration. After migration, the processor page table pointer is switched to point to the first page table. A page entry in the second page table corresponding to a page entry made to the first page table by the logical partition may be invalidated in response to a page table hypervisor call made by the logical partition. In parallel, a plurality of entries generated during the migration of the logical partition in the second page table may be read through and invalidated.Type: GrantFiled: April 16, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Stuart Zachary Jacobs, David Anthony Larson, Naresh Nayar, Jonathan Ross Van Niewaal, Kenneth Charles Vossen
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Patent number: 8019962Abstract: An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.Type: GrantFiled: April 16, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: William Joseph Armstrong, Michael J. Corrigan, Stuart Zachary Jacobs, David Anthony Larson, Naresh Nayar, Wade Byron Ouren
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Patent number: 7673114Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity at the request of a logical partition to help the logical partition determine whether a reallocation of resources between nodes may improve memory affinity for the logical partition. If so, the logical partition requests reallocation of resources by the dynamic partition manager so memory affinity for the logical partition is improved.Type: GrantFiled: January 19, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Kenneth Roger Allen, William Anton Brown, Stuart Zachary Jacobs, Wade Bryon Ouren, Kenneth Charles Vossen
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Publication number: 20080256327Abstract: An apparatus, program product and method maintains data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target computer system. A first page table may be configured to store a plurality of page entries made within a logically partitioned environment. A second page table may be used during migration to store one or more page entries generated during the migration. After migration, the processor page table pointer may be transparently switched to point to the first page table. A page entry in the second page table corresponding to a page entry made to the first page table by the logical partition may be invalidated in response to a page table hypervisor call made by the logical partition. In parallel, a plurality of entries generated during the migration of the logical partition in the second page table may be read through and invalidated.Type: ApplicationFiled: April 16, 2007Publication date: October 16, 2008Inventors: Stuart Zachary Jacobs, David Anthony Larson, Naresh Nayar, Jonathan Ross Van Niewaal, Kenneth Charles Vossen
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Publication number: 20080256321Abstract: An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.Type: ApplicationFiled: April 16, 2007Publication date: October 16, 2008Inventors: William Joseph Armstrong, Michael J. Corrigan, Stuart Zachary Jacobs, David Anthony Larson, Naresh Nayar, Wade Byron Ouren