Patents by Inventor Su Chun-Jen

Su Chun-Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020173074
    Abstract: A method for underfilling bonding gap between flip-chip and circuit substrate is disclosed. A chip is mounted on a circuit substrate with flip-chip configuration. The circuit substrate has a top surface, a bottom surface, and a plurality of via holes. Some of the via holes are formed to be air vents passing through the top surface and the bottom surface. So that the underfill material flows into the gap between flip-chip and circuit substrate until jamming or blocking the said air vents rapidly while underfilling.
    Type: Application
    Filed: May 16, 2001
    Publication date: November 21, 2002
    Applicant: Walsin Advanced Electronics LTD
    Inventors: Su Chun-Jen, Lai Chien-Hung, Lin Chien-Tsun, Chang Chao-Chia
  • Patent number: 6459148
    Abstract: A QFN semiconductor package comprises a semiconductor die, a lead frame, bonding wires and a molding compound. The die has an upward topside with a plurality of bonding pads. The lead frame consists of a plurality of inner leads, wherein each inner lead is divided into the front finger portion, the middle protruding portion and the rare connecting portion. The front finger portion is the position of the inner lead to which a bonding wire wire-bonds from the bonding pad of the die. The rare connecting portion is for the electrical out-connection of the package. The middle protruding portion is at height level higher than the front finger portion and the rare connecting portion. The bonding wires electrically connect the bonding pads of the die with the front finger portions of inner leads by means of wire-bonding.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: October 1, 2002
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Su Chun-Jen, Lin Chien-Tsun, Chang Chao-Chia, Su Yu-Hsien, Tseng Ming-Hui
  • Patent number: 6385049
    Abstract: A multi-board BGA package comprises a chip, a plurality of circuit boards, a plurality of metal bonding wires, a plurality of solder balls, and a package body. The circuit boards are formed on a same plane. Between adjacent circuit boards there is a galley for passing through metal bonding wires to connect chip with circuit board and molding package body easily. The plurality of circuit boards together hold the chip so as to reduce thermal stress caused by CTE mismatch.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: May 7, 2002
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Hung Chia-Yu, Su Chun-Jen, Lai Chien-Hung
  • Patent number: 6337510
    Abstract: A stackable QFN semiconductor package comprises a die, a lead frame, an electrical connection device, and a molding compound. The die has a plurality of bonding pads on its topside. The lead frame consists of a plurality of inner leads around edge of the die and each inner lead is divided into the body and the finger extending from the body. The body is thicker than the die and exposes its upper surface and lower surface for outer electrical connection of the package. The finger extends from the body to above the topside of the die. An electrical connection device connects the bonding pad of die and the finger of inner lead, thus electrically connect the die and the inner lead of lead frame. A molding compound seals around outer edge of the inner lead and seals off at least said electrical connection device; therefore provide ability of stack, thinner package and simplicity.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: January 8, 2002
    Assignee: Walsin Advanced Electronics LTD
    Inventors: Su Chun-Jen, Lin Chien-Tsun, Chang Chao-Chia, Su Yu-Hsien, Tseng Ming-Hui