Patents by Inventor Suangwu Huang
Suangwu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7553697Abstract: A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: November 9, 2006Date of Patent: June 30, 2009Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 7485562Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: January 3, 2005Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Patent number: 7173330Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: June 30, 2005Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 7087992Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: November 30, 2004Date of Patent: August 8, 2006Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Patent number: 6987031Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 27, 2002Date of Patent: January 17, 2006Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 6964881Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: August 27, 2002Date of Patent: November 15, 2005Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou
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Patent number: 6958537Abstract: A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.Type: GrantFiled: August 4, 2004Date of Patent: October 25, 2005Assignee: Micron Technology, Inc.Inventors: Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang
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Patent number: 6825553Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.Type: GrantFiled: September 5, 2003Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou