Abstract: A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

Abstract: A memory control device implements split storage of user-data and metadata components of a compound write data word, outputting the user-data component via a memory control interface for storage within an external memory subsystem while separately storing the metadata component within a metadata cache implemented within the memory control device.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.

Abstract: A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: Systems and methods are provided that enable flow aware buffer management. The method includes storing in a queue of a buffer a first type of traffic, storing in the queue of the buffer a second type of traffic, wherein the first type of traffic is less sensitive to latency than the second type of traffic, and when an amount of the first type of traffic meets or exceeds a first threshold, effecting flow control of the first type of traffic to slow a flow of the first type of traffic into the buffer. Flow control can be effected using packet marking or discarding packets. The methodology has particular utility in connection with managing elephant and mouse flows in a network switch.

Abstract: A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Abstract: Systems and methods are provided that enable flow aware buffer management. The method includes storing in a queue of a buffer a first type of traffic, storing in the queue of the buffer a second type of traffic, wherein the first type of traffic is less sensitive to latency than the second type of traffic, and when an amount of the first type of traffic meets or exceeds a first threshold, effecting flow control of the first type of traffic to slow a flow of the first type of traffic into the buffer. Flow control can be effected using packet marking or discarding packets. The methodology has particular utility in connection with managing elephant and mouse flows in a network switch.

Abstract: An input/output (IO) device for connecting multiple servers to one or more network interfaces. The device includes a network connection module comprising one or more network interfaces, and a virtual host interface configured to enable communication with a plurality of host servers. The device includes IO controller configured to connect each of the host servers to one or more of the network interfaces such that the connections between each host server and corresponding one or more network interfaces are operationally isolated and independent from one another.

Abstract: A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Abstract: An apparatus and related methods are provided to greatly reduce the negative impact of head of line (HOL) blocking. At a device (e.g., switch, router, etc.) configured to forward packets in a network, new packets that are to be forwarded from the device to other devices in the network are stored in a memory of the device. Entries are added to a queue link list for the at least one queue as new packets are added to the at least one queue. A detection is made when the at least one queue exceeds a threshold indicative of head of line blocking. For new packets that are to be added to the at least one queue, entries are added to a sub-queue link list for the plurality of sub-queues such that packets are assigned to different ones of a plurality of sub-queues when the at least one queue exceeds the threshold. Packets are output from the memory for the plurality of sub-queues according to the sub-queue link list.

Abstract: An input/output (IO) device for connecting multiple servers to one or more network interfaces. The device includes a network connection module comprising one or more network interfaces, and a virtual host interface configured to enable communication with a plurality of host servers. The device includes IO controller configured to connect each of the host servers to one or more of the network interfaces such that the connections between each host server and corresponding one or more network interfaces are operationally isolated and independent from one another.

Abstract: Dynamic load balancing techniques among ports of a network device are provided. At a device configured to forward packets in a network, a plurality of queues are generated, each associated with a corresponding one of a plurality of output ports of the device and from which packets are to be output from the device into the network. When the number of packets in the at least one queue exceeds a threshold, for new packets that are to be enqueued to the at least one queue, packets are enqueued to a plurality of sub-queues such that packets are assigned to different ones of the plurality of sub-queues. Each of the plurality of sub-queues is associated with a corresponding one of the plurality of output ports. Packets of the plurality of sub-queues are output from corresponding ones of the plurality of output ports.

Abstract: In one embodiment, a method includes receiving a multi-destination packet at a switch in communication with a plurality of servers through a network device, identifying a port receiving the multi-destination packet at the switch or a forwarding topology for the multi-destination packet, selecting a bit value based on the identified port or forwarding topology, inserting the bit value into a field in a virtual network tag in the multi-destination packet, and forwarding the multi-destination packet with the virtual network tag to the network device. The network device is configured to forward the multi-destination packet to one or more of the servers based on the bit value in the multi-destination packet. An apparatus for forwarding multi-destination packets is also disclosed.

Abstract: An apparatus and related methods are provided to greatly reduce the negative impact of head of line (HOL) blocking. At a device (e.g., switch, router, etc.) configured to forward packets in a network, new packets that are to be forwarded from the device to other devices in the network are stored in a memory of the device. Entries are added to a queue link list for the at least one queue as new packets are added to the at least one queue. A detection is made when the at least one queue exceeds a threshold indicative of head of line blocking. For new packets that are to be added to the at least one queue, entries are added to a sub-queue link list for the plurality of sub-queues such that packets are assigned to different ones of a plurality of sub-queues when the at least one queue exceeds the threshold. Packets are output from the memory for the plurality of sub-queues according to the sub-queue link list.