Abstract: A system and process to adjust the transmission rate of data packets by measuring (continuously or at pre-set intervals) certain elements and variables to reliably measure the current transmission rate and gaps (wasted space) to determine the channel utilization. These measurements are used to adjust the transmission rate of data in real time. The measurement of these variables reliably predicts the optimum transmission rate and can adjust the same to both efficiently transmit data and avert network congestion. A communication processing device comprising one or more processors operable to measure inter-packet gap times to estimate and utilize channel capacity changes during transmission.

Abstract: A system and process to adjust the transmission rate of data packets by measuring (continuously or at pre-set intervals) certain elements and variables to reliably measure the current transmission rate and gaps (wasted space) to determine the channel utilization. These measurements are used to adjust the transmission rate of data in real time. The measurement of these variables reliably predicts the optimum transmission rate and can adjust the same to both efficiently transmit data and avert network congestion. A communication processing device comprising one or more processors operable to measure inter-packet gap times to estimate and utilize channel capacity changes during transmission.

Abstract: Methods, systems, and apparatuses related to a communication switch are disclosed herein. In some embodiments, the communication switch may be configured to transmit TDM, ATM and/or packet data from an ingress service processor, through a plurality of switch elements, to an egress service processor. Other embodiments may be described and claimed.

Abstract: Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Abstract: A method for the fair and efficient transfer of variable length packets using fixed length “segments” utilizes a modified UTOPIA interface with three additional signals added, i.e. start of packet (SOP), end of packet (EOP), and most significant byte (MSB). Packets are broken into “segments” of fixed, but programmable, length. The start of a segment is marked by a pulse on the UTOPIA start of cell (SOC) signal line. The start of a packet is marked by a pulse on the SOP signal line. The end of a packet is marked by a pulse on the EOP signal line. According to a presently preferred embodiment, bytes are transferred via a 16-bit bus. When a packet ends with a single byte on the bus, the MSB signal line is asserted to distinguish it from a packet which ends with two bytes on the bus. The invention can be expanded to accommodate buses wider than 16-bits by making the EOP a multiple bit signal.

Abstract: A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register.

Abstract: A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register.

Abstract: Methods for managing multiple queues of ATM cells in shared RAM while efficiently supporting multicasting include providing a common memory for storing ATM cells and for storing at least one pointer to each ATM cell stored, providing a management memory for storing an index to the pointers stored in common memory, a table for each multicast session, and an index to the free space in common memory. According to the presently preferred method, cells entering the switch are examined, placed in shared RAM, and a pointer to the RAM location is written in another location in the shared RAM. Table entries in management RAM are updated each time a cell is added to a queue. When a multicast session is begun, a multicast table is created with all of the addresses in the multicast session. When a multicast cell is received, the multicast session table is consulted and pointers to the cell are copied to queues for each address in the table.

Abstract: The apparatus includes a separate line side inlet queue for each GFR VC, a single network side outlet queue for all GFR VCs, a single network side inlet queue for all GFR VCs, a single line side outlet bulk processing queue with a post queue packet processor followed by separate line side outlet queues for each line, a network side outlet queue monitor, and a line side inlet queue controller. The network side outlet queue monitor is coupled to the line side inlet queue controller so that the network side outlet queue monitor can send messages to the line side inlet queue controller. According to one of the methods of the invention, the network side outlet queue monitor sends messages to the line side inlet queue controller directing the line side inlet queue controller to send data from the line side GFR queues based on the status of the network side outlet GFR queue. According to another method of the invention, the line to side inlet queue controller discards packets for a GFR VC if congestion is indicated.

Abstract: An ATM switch system has a plurality of input ports and output ports all having associated buffers, and a source traffic control system which includes a shared bus coupling the ports, and a switch controller or arbiter which controls the transfer of data among the ports via the shared bus. ATM cells placed on the shared bus include an internal destination address which designates the output port within the switch to which the ATM cell is destined. The switch controller monitors the internal destination addresses of the ATM cells, and increments a counter associated with the destination port when the destination corresponds, and decrements other counters which do not correspond to the destination. Accordingly, bursts for a particular output port causes the count of the associated counter to grow large; whereas frequent or long breaks cause the count to drop. The counts are compared to a high threshold which alerts the arbiter that the buffer of the output port being tracked is in danger of overflowing.

Abstract: A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N.times.32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles.

Abstract: Apparatus and methods for allocating shared memory utilizing linked lists are provided which are particularly useful in telecommunications applications such as ATM. A management RAM contained within a VLSI circuit is provided for controlling the flow of data into and out of a shared memory (data RAM), and stores information regarding a number of link lists and a free link list in the shared memory, and a block pointer to unused RAM locations. A head pointer, tail pointer, block counter and empty flag are stored for each data link list. The head and tail pointers each include a block pointer and a position counter. The block counter contains the number of blocks used in the particular queue. The empty flag indicates whether the queue is empty. The free link list includes a head pointer, a block counter, and an empty flag. Each memory page of the shared data RAM receiving the incoming data includes locations for storing data.

Abstract: An ATM destination switch includes an ATM layer device coupled to a physical layer device. The ATM layer device includes a ATM layer interface which receives incoming ATM cells, a processor which is typically with an associated translation RAM, and an ATM layer to physical layer interface. The processor decodes the incoming ATM cell to obtain a VPI/VCI, and provides additional routing information (session number) for the cell for multicast purposes. The cell with the additional routing information is forwarded to the physical layer device which has a header processor, a multicast indicator storage table, preferably in the form of a bit map, for storing output line indications by session number, and a plurality of ATM line output interfaces.