Patents by Inventor Subhash Gupta

Subhash Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7452808
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 18, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20060280698
    Abstract: A system for treating conditions of the periodontium, such as gingivitis and periodontitis, includes an Ayurvedic medicinal solution and an applicator for delivering the solution to the periodontium. The Ayurvedic medicinal solution utilizes herbal extracts to break-down bacteria which can inflame gum tissue. In one embodiment, the solution comprises approximately 1 gram of triphala extract for every 10 ml of glycerine. In another embodiment, the solution comprises approximately 1 gram of amla extract for every 10 ml of glycerine. The applicator for delivering the solution to the periodontium may either be in the form of a cotton swab-type wand, a pipette or a spray dispenser.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 14, 2006
    Inventors: Subhash Gupta, Dennis Flanagan
  • Patent number: 7060613
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: June 13, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Xu Yi
  • Patent number: 6967162
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 22, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20050224921
    Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 13, 2005
    Inventors: Subhash Gupta, Paul Ho, Sangki Hong
  • Publication number: 20050181081
    Abstract: The present invention provides an improved preparation based on the synergistic action of garlic extract and essential oil of M. spicata var. Ganga or cinnamon oil against dermatophytic fungus. More particularly, the present invention relates to the synergistic enhancement of activity of a combination by menthyl acetate or Geraniol. The invention also provides a method of preparation of the synergistic combination and the shelf life observed to be more than one year. The cream based preparation is a potent anti-dermatophytic as described and illustrated by in vitro and in vivo evaluations.
    Type: Application
    Filed: January 21, 2004
    Publication date: August 18, 2005
    Inventors: Suman Khanuja, Pushplata Chaturvedi, Anil Singh, Ajit Shasany, Vinay Agarwal, Vivek Gupta, Subhash Gupta, Arun Tripathy, Anirban Pal, Dharmendra Saikia, Mahendra Darokar, Krishna Aggarwal, Ravi Bansal
  • Publication number: 20050112799
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 26, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu
  • Publication number: 20050100610
    Abstract: The invention relates to a novel pharmaceutical composition comprising an effective amount of bio-active fraction from cow urine distillate as a bioavailability facilitator and pharmaceutically acceptable additives selected from anticancer compounds, antibiotics, drugs, therapeutic and nutraceutic agents, ions and similar molecules which are targeted to the living systems.
    Type: Application
    Filed: April 13, 2004
    Publication date: May 12, 2005
    Applicant: COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH RAFI MARG
    Inventors: Suman Khanuja, Sushil Kumar, Ajit Shasany, Jai Arya, Mahendra Darokar, Monika Singh, Prachi Sinha, Soumya Awasthi, Subhash Gupta, Vivek Gupta, Madan Gupta, Ram Verma, Sweta Agarwal, Sunil Mansinghka, Suresh Dawle
  • Publication number: 20050090037
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: October 29, 2004
    Publication date: April 28, 2005
    Inventors: Yakub Aliyu, Simon Chooi, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy
  • Publication number: 20050090102
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: April 28, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20050090039
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: April 28, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Patent number: 6821888
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6813796
    Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6740580
    Abstract: A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: May 25, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Chyi S. Chern, Mei Sheng Zhou
  • Publication number: 20040082169
    Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of single or dual damascene interconnects using a barrier metal layer of WNx or TaNx, deposited by plasma enhanced chemical vapor deposition (PECVD) using metal carbonyl precursors. By using a chemical vapor deposition (CVD) process with these alternate carbonyl precursors, many of the problems are solved, i.e., conformal coverage, gas phase particle generation, and incorporation of halogens or carbon into the film.
    Type: Application
    Filed: October 29, 2002
    Publication date: April 29, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Mei Sheng Zhou, Subhash Gupta
  • Patent number: 6720204
    Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 13, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6705512
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 16, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6692579
    Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: February 17, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
  • Patent number: 6683002
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: January 27, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: RE39518
    Abstract: It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: March 13, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony John Toprac, Douglas John Downey, Subhash Gupta