Patents by Inventor Subhashis Mandal

Subhashis Mandal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10534887
    Abstract: A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 14, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sravasti Nair, Subhashis Mandal, Chandra Prakash Manglani, Nikhil Garg, Preeti Kapoor, Kanaka Raju Gorle
  • Patent number: 10452807
    Abstract: Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 22, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karun Sharma, Nikhil Garg, Juno Jui-Chuan Lin, Subhashis Mandal, Chandra Prakash Manglani, Kanaka Raju Gorle, Henry Yu
  • Patent number: 10402530
    Abstract: Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout circuit components with the row template.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karun Sharma, Yu Liu, Subhashis Mandal, Kanaka Raju Gorle, Jeff Taraldson