Abstract: The voltage outputs of a charge coupled device (CCD) are examined to determine the hot pixels. A black pixel is determined to be a hot pixel if the voltage level associated with the black pixel exceeds the voltage level of an adjacent (e.g., previous) pixel by a threshold. If the present black pixel is determined to be a hot pixel, a previous black pixel is substituted for a present black pixel in the computation of the offset. However, if the first black pixel is determined to be a hot pixel, the second black pixel is used in lieu of the first black pixel. The offset is iteratively adjusted by an amount proportionate to an error determined based on the black pixels. The adjustment may be clipped by a threshold to avoid bands in the image.

Abstract: An offset correction circuit which enables a designer to control the correction range irrespective of the amplification sought to be achieved to the image component of the input signal. The offset correction further enables the designer to perform offset correction to a low resolution. Both range and resolution can potentially be attained using only two stages thereby minimizing power consumption and also minimizing introduction of any undesirable components.

Abstract: An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor 32 is coupled between the negative input node and an analog signal node. A second capacitor 34 is coupled between the positive input node and a reference voltage node. In addition, a third capacitor 36 is coupled between the positive input node and the negative output node and a fourth capacitor 38 is coupled between the negative input node and the positive output node. A first switch 40 is coupled between the third capacitor 36 and the negative output node and a second switch 42 is coupled between the fourth capacitor 38 and the positive output node. An inverter coupled to the analog signal node drives common mode capacitors coupled between the output of the inverter and the respective negative and positive input nodes.

Abstract: An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage amplifier 62. The comparator 70 also includes additional capacitors 82 and 83 coupled between the inputs of the preamplifier 78 and reference voltage nodes VREFP and VREFM. Switches 73 and 74 are coupled between the additional capacitors 82 and 83 and the reference voltage nodes VREFP and VREFM. An additional switch 72 is coupled between the additional capacitors 82 and 83. In this configuration, there are no series sampling switches between the previous stage amplifier 62 and the comparator 70. Eliminating the series switches reduces the load seen by the previous stage amplifier 62, which allows the previous stage amplifier 62 to have a faster settling time. This allows the current in the previous stage amplifier 62 to be decreased which reduces the power consumption.

Abstract: An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor 32 is coupled between the negative input node and an analog signal node. A second capacitor 34 is coupled between the positive input node and a reference voltage node. In addition, a third capacitor 36 is coupled between the positive input node and the negative output node and a fourth capacitor 38 is coupled between the negative input node and the positive output node. A first switch 40 is coupled between the third capacitor 36 and the negative output node and a second switch 42 is coupled between the fourth capacitor 38 and the positive output node.

Abstract: A system is provided for enabling single ended to differential conversion of signal. The system includes N serially coupled amplifier stages, wherein N is an integer, for receiving a single ended input signal, wherein each of the N amplifier stages shifts an input signal from the previous stage to a reference associated with each of the N amplifier stages to provide a non-distorted differential output signal at the output of the Nth amplifier stage.

Abstract: An amplifier, preferably an integrated circuit, capable of accepting input common mode voltages below the circuit reference voltage or substrate voltage in the case of an integrated circuit. The amplifier comprises a differential voltage input having higher and lower voltage terminals, a first NMOS transistor coupled between a voltage supply and the higher voltage terminal and a second NMOS transistor coupled between the voltage supply and the lower voltage terminal. A third NMOS transistor is coupled between the voltage supply and the first transistor gate, a fourth NMOS transistor is coupled between the voltage supply and the second transistor gate and a sink resistor is coupled between the gate of the second transistor and the lower voltage terminal. A differential resistor is coupled between the gates of the first and second transistors.