Patents by Inventor Subodh Taigor

Subodh Taigor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast settling low dropout voltage regulator
    Patent number: 9939831
    Abstract: Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a controller and then is ended when the output voltage of the voltage regulator is within a first voltage of the desired regulation voltage or has overshot the desired regulation voltage by a second voltage (e.g., has overshot the desired regulation voltage by 150 mV).
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: April 10, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Saurabh Verma, Subodh Taigor, Sridhar Yadala
  • FAST SETTLING LOW DROPOUT VOLTAGE REGULATOR
    Publication number: 20170199536
    Abstract: Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a controller and then is ended when the output voltage of the voltage regulator is within a first voltage of the desired regulation voltage or has overshot the desired regulation voltage by a second voltage (e.g., has overshot the desired regulation voltage by 150 mV).
    Type: Application
    Filed: January 11, 2016
    Publication date: July 13, 2017
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Saurabh Verma, Subodh Taigor, Sridhar Yadala
  • Active regulator wake-up time improvement by capacitive regulation
    Patent number: 8981750
    Abstract: An active voltage regulator circuit having improved wake-up response is presented. The circuit includes an op-amp whose output is connected to a pass device for supplying the output level, and has both capacitive and resistive parts in its feedback loop. When the regulator is enabled, the capacitive elements are initially connected, followed after a delay by the resistive elements of the feedback loop.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: March 17, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Kumar Meher, Sridhar Yadala, Subodh Taigor
  • Active Regulator Wake-Up Time Improvement by Capacitive Regulation
    Publication number: 20150054480
    Abstract: An active voltage regulator circuit having improved wake-up response is presented. The circuit includes an op-amp whose output is connected to a pass device for supplying the output level, and has both capacitive and resistive parts in its feedback loop. When the regulator is enabled, the capacitive elements are initially connected, followed after a delay by the resistive elements of the feedback loop.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Deepak Kumar Meher, Sridhar Yadala, Subodh Taigor