Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.

Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.

Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.

Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.

Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.

Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.

Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.

Abstract: One example includes a master microcontroller in a communication interface system. The microcontroller includes a transmitter configured to generate a clock signal at a selected frequency and to provide the clock signal to a slave microcontroller on a two-wire communication cable during a clock learning mode. The transmitter can be further configured to provide master data signal requests at the selected frequency on the two-wire communication cable during a data transfer mode. The microcontroller also includes a receiver configured to receive slave data signals at the variable frequency via the two-wire communication cable in response to the master data signal requests during the data transfer mode.

Abstract: One example includes a master microcontroller in a communication interface system. The microcontroller includes a transmitter configured to generate a clock signal at a selected frequency and to provide the clock signal to a slave microcontroller on a two-wire communication cable during a clock learning mode. The transmitter can be further configured to provide master data signal requests at the selected frequency on the two-wire communication cable during a data transfer mode. The microcontroller also includes a receiver configured to receive slave data signals at the variable frequency via the two-wire communication cable in response to the master data signal requests during the data transfer mode.

Abstract: A system includes a CPU, a serial interface, and an adaptive clock delay compensator. The adaptive clock delay compensator is configured to generate a clock signal at a first frequency, detect an edge on a data signal, and count the number of clock cycles of a counter clock to measure the delay between an edge of the clock signal and the detected edge on the data signal to produce a first delay value. The CPU is configured to convert the first delay value to a different clock domain at a second frequency to produce a converted delay value, and initiate a data transfer operation using the second frequency as a clock signal. The adaptive clock delay compensator is configured to generate a delayed clock signal at the second frequency to the serial interface that is delayed from the clock signal at the second frequency by the converted delay value.

Abstract: A system includes a CPU, a serial interface, and an adaptive clock delay compensator. The adaptive clock delay compensator is configured to generate a clock signal at a first frequency, detect an edge on a data signal, and count the number of clock cycles of a counter clock to measure the delay between an edge of the clock signal and the detected edge on the data signal to produce a first delay value. The CPU is configured to convert the first delay value to a different clock domain at a second frequency to produce a converted delay value, and initiate a data transfer operation using the second frequency as a clock signal. The adaptive clock delay compensator is configured to generate a delayed clock signal at the second frequency to the serial interface that is delayed from the clock signal at the second frequency by the converted delay value.

Abstract: A selected-parameter adaptively switched power conversion system, for example, includes a counter for determining a period of an output oscillation a power supply switch, where the output oscillation starts when an output current generated by stored power of the power supply coil decays substantially to zero. An event generator for generating a switching delay event in response to the determined output oscillation period and generates a switching delay event in response to a determination of a phase of the output oscillation.

Abstract: A selected-parameter adaptively switched power conversion system, for example, includes a counter for determining a period of an output oscillation a power supply switch, where the output oscillation starts when an output current generated by stored power of the power supply coil decays substantially to zero. An event generator for generating a switching delay event in response to the determined output oscillation period and generates a switching delay event in response to a determination of a phase of the output oscillation.

Abstract: A selected-parameter adaptively switched power conversion system, for example, includes a counter for determining a period of an output oscillation a power supply switch, where the output oscillation starts when an output current generated by stored power of the power supply coil decays substantially to zero. An event generator for generating a switching delay event in response to the determined output oscillation period and generates a switching delay event in response to a determination of a phase of the output oscillation.