Patents by Inventor Subramanian Ganesan

Subramanian Ganesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220253583
    Abstract: This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously with the first SVP and transmits data to the first SVP while simulating the first portion of the circuit design, wherein the first SVP uses the data while simulating the first portion of the circuit design.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 11, 2022
    Inventors: Subramanian GANESAN, Ramesh NARAYANASWAMY, Dinesh Madusanke PASIKKU HANNADIGE, Chanaka RANATHUNGA, Aditha Pabasara RAJAKARUNA, Subha Sankar CHOWDHURY
  • Publication number: 20220198120
    Abstract: A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 23, 2022
    Inventors: Ramesh NARAYANASWAMY, Subramanian GANESAN, Dinesh Madusanke PASIKKU HANNADIGE
  • Patent number: 9870282
    Abstract: Systems and methods for providing service and to computing devices. In some embodiments, an Information Handling System (IHS) includes a Basic I/O System (BIOS) and a memory coupled to the BIOS, the memory including program instructions stored thereon that, upon execution by the IHS, cause the IHS to: determine that the IHS is operating in a degraded state; and initiate one or more support, diagnostics, or remediation operations in response to the determination.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: January 16, 2018
    Assignee: Dell Products, L.P.
    Inventors: Todd Erick Swierk, Carlton A. Andrews, Bruce C. Bell, Michael Todd Boyum, Subramanian Ganesan, Yuan-Chang Lo, Phillip M. Seibert
  • Publication number: 20160335151
    Abstract: Systems and methods for providing service and to computing devices. In some embodiments, an Information Handling System (IHS) includes a Basic I/O System (BIOS) and a memory coupled to the BIOS, the memory including program instructions stored thereon that, upon execution by the IHS, cause the IHS to: determine that the IHS is operating in a degraded state; and initiate one or more support, diagnostics, or remediation operations in response to the determination.
    Type: Application
    Filed: May 11, 2015
    Publication date: November 17, 2016
    Applicant: Dell Products, L.P.
    Inventors: Todd Erick Swierk, Carlton A. Andrews, Bruce C. Bell, Michael Todd Boyum, Subramanian Ganesan, Yuan-Chang Lo, Phillip M. Seibert
  • Patent number: 9100396
    Abstract: A system, method, and computer-readable medium are disclosed for managing a system's entitlement to digital assets when the system's components are replaced. A unique system identifier, comprising the unique identifiers of predetermined system components, is associated with digital assets data to generate digital assets entitlement data, which in turn entitles the system to process the digital assets data. The digital assets entitlement is perpetuated when a first unique system component identifier is replaced with a second unique system component identifier.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 4, 2015
    Assignee: Dell Products L.P.
    Inventors: Clint H. O'Connor, Gary D. Huber, Michael Haze, William A. Curtis, Brian Decker, Frank Molsberry, Subramanian Ganesan
  • Patent number: 8850381
    Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Subramanian Ganesan, Philip Henry Nils Anthony De Buren, Jinny Singh, David Abada
  • Patent number: 8799933
    Abstract: An apparatus for providing remote services to an integrated information technology environment. The apparatus comprises a remote management platform. The remote management platform comprises a service delivery platform which comprises a plug in module. The plug in module is configurable to comprise a plurality of service functions. The plug in module enables some or all of the plurality of service functions to be selectively enabled.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: August 5, 2014
    Assignee: Dell Products L.P.
    Inventors: Rajveer Singh Kushwaha, Stephen Francis Schuckenbrock, Timothy Abels, Subramanian Ganesan
  • Patent number: 8595683
    Abstract: A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: November 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Philip H. de Buren, Subramanian Ganesan, Jinny Singh
  • Patent number: 8176150
    Abstract: A system which enables a secure network boot to address customer services offerings. The customer service offerings can include on-demand diagnostics to system reinstallation as well as automatic entitlement validation and service installation. Such a system enables a method of network booting that can be secure from beginning to end, is routable in any network configuration that supports Internet routing, avoids traditional infrastructure requirements thereby making the infrastructure more accessible, is extensible to address scaling requirements, is extensible to EFI technology and can be used on existing BIOS option-ROM implementations, provides a better (i.e., simpler, more secure) customer experience for network boot services, provides a multi-stage architecture that allows numerous service offerings to be obtained once entitlement is validated, and provides for both In-Band (OS operational and booted) and Out-of-Band (OS not operational or not installed) access to remote service capabilities.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 8, 2012
    Assignee: Dell Products L.P.
    Inventors: Mark Collins, Subramanian Ganesan
  • Publication number: 20110191863
    Abstract: A system, method, and computer-readable medium are disclosed for managing a system's entitlement to digital assets when the system's components are replaced. A unique system identifier, comprising the unique identifiers of predetermined system components, is associated with digital assets data to generate digital assets entitlement data, which in turn entitles the system to process the digital assets data. The digital assets entitlement is perpetuated when a first unique system component identifier is replaced with a second unique system component identifier.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 4, 2011
    Inventors: Clint H. O'Connor, Gary D. Huber, Michael Haze, William A. Curtis, Brian Decker, Frank Molsberry, Subramanian Ganesan
  • Publication number: 20110040857
    Abstract: A system which enables a secure network boot to address customer services offerings. The customer service offerings can include on-demand diagnostics to system reinstallation as well as automatic entitlement validation and service installation. Such a system enables a method of network booting that can be secure from beginning to end, is routable in any network configuration that supports Internet routing, avoids traditional infrastructure requirements thereby making the infrastructure more accessible, is extensible to address scaling requirements, is extensible to EFI technology and can be used on existing BIOS option-ROM implementations, provides a better (i.e., simpler, more secure) customer experience for network boot services, provides a multi-stage architecture that allows numerous service offerings to be obtained once entitlement is validated, and provides for both In-Band (OS operational and booted) and Out-of-Band (OS not operational or not installed) access to remote service capabilities.
    Type: Application
    Filed: August 12, 2009
    Publication date: February 17, 2011
    Inventors: Mark Collins, Subramanian Ganesan
  • Publication number: 20090187929
    Abstract: An apparatus for providing remote services to an integrated information technology environment. The apparatus comprises a remote management platform. The remote management platform comprises a service delivery platform which comprises a plug in module. The plug in module is configurable to comprise a plurality of service functions. The plug in module enables some or all of the plurality of service functions to be selectively enabled.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 23, 2009
    Inventors: Rajveer Singh Kushwaha, Stephen Francis Schuckenbrock, Timothy Abels, Subramanian Ganesan
  • Patent number: 5636130
    Abstract: A method is provided for accurately determining the propagation delay of a gate under consideration in a static timing analyzer. This is accomplished by determining both the output load and input rise time of the gate under consideration. These values are then compared with a load versus rise time grid having previously determined values of propagation delay (points) for specified combinations of load and input rise time. These points are then used to interpolate a value of propagation delay for the gate under consideration by an interpolation technique that accounts for at least one of the following non-linear effects: the feed forward capacitance of a gate, soft switching, gate resistance, source and drain resistance, and/or other non-linear effects. The method accounts for each non-linear effect by imparting a corresponding component to propagation delay only in that range of output load and input rise time for which that non-linear effect is most pronounced.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: June 3, 1997
    Assignee: Sun Microsystems, Inc.
    Inventors: Raoul B. Salem, Vernon R. Brethour, Wen-Jay Hsu, Raymond A. Heald, Subramanian Ganesan