Abstract: An electronic device may be provided with a phased antenna array that radiates at a frequency greater than 10 GHz through a display. The array may include a dielectric resonator antenna having a dielectric column. The dielectric column may have a first surface mounted to a circuit board and a second surface that faces the display. A conductive cap may be formed on the second surface. The conductive cap may allow the dimensions of dielectric column to be reduced while still allowing the dielectric resonator antenna to cover a frequency band of interest. If desired, the phased antenna array may include multiple sets of dielectric resonator antennas for covering different frequency bands. The sets may have different dielectric column heights and/or different conductive cap sizes.

Abstract: An electronic device may be provided with a phased antenna array that radiates at a frequency greater than 10 GHz. The array may include a dielectric resonator antenna having a dielectric column with non-planar sidewalls that include planar portions and corrugated portions with grooves and ridges, that include sidewall steps, and/or that include angled sidewall portions. The dielectric resonator antenna may include a first dielectric column and a second dielectric column stacked on the first dielectric column. The second column may be narrower and may have a higher dielectric constant than the first column or may have the same width but a lower dielectric constant than the first column. This may serve to broaden the bandwidth of the dielectric resonator antenna relative to scenarios where the dielectric resonator antenna includes only a single dielectric resonating element having only planar sidewalls.

Abstract: An electronic device may be provided with a phased antenna array that radiates at a frequency greater than 10 GHz. The array may include a first set of dielectric resonator antennas arranged in a first row and a second set of dielectric resonator antennas in a second row offset from the first row. Each dielectric resonator antenna may have dielectric resonating element with a base portion and a stepped portion. The stepped portions of the antennas in the first set may be arranged to be distant from the stepped portions of the antennas in the second set. The antennas in the first set may be arranged to be more distant from an electronic device sidewall than the antennas in the second set. Configured in this manner, the array may exhibit reduced inter-coupling between dielectric resonator antennas in the first set and dielectric resonator antennas in the second set.

Abstract: An electronic device may include an antenna and a coaxial cable coupled to the antenna. The coaxial cable may have a signal conductor coupled to an antenna resonating element of the antenna and a ground conductor coupled to an antenna ground of the antenna. The ground conductor may include an ungrounded segment that is separated from the antenna ground by a gap. A capacitive coupling between the ground conductor in the ungrounded segment and the antenna ground via the gap may form an impedance matching component for the coaxial cable. A dielectric retention layer may overlap the coaxial cable and hold the coaxial cable in place relative to the antenna ground to maintain the gap.

Abstract: An electronic device may be provided with a phased antenna array having a dielectric resonator antenna. The antenna may include a first dielectric block on a printed circuit, a second dielectric block on the first dielectric block, and a third dielectric block on the second dielectric block. At least the second and third dielectric blocks may have different dielectric constants. The antenna may be fed by one or more feed probes. Each feed probe may include respective conductive via and a conductive patch coupled to the conductive via. The conductive via may extend through the first dielectric block. The conductive patch may be sandwiched between the first and second dielectric blocks. The conductive patch may have a width that configures the conductive patch to form a smooth impedance transition between the conductive via and each of the dielectric blocks despite the different materials used to form the antenna.

Abstract: An electronic device may be provided with a phased antenna array having a dielectric resonator antenna. The antenna may include a first dielectric block on a printed circuit, a second dielectric block on the first dielectric block, and a third dielectric block on the second dielectric block. At least the second and third dielectric blocks may have different dielectric constants. A parasitic element may be disposed between the second and third dielectric resonating elements and/or a parasitic element may be disposed on a radiative face of the third dielectric resonating element. The parasitic elements may act as electromagnetic mirrors that form images of electric fields in the dielectric resonating elements. The images may make the dielectric resonating elements exhibit a greater electromagnetic height than physical height. This may allow for a reduction in the overall physical height of the dielectric resonator antenna without sacrificing wireless performance.

Abstract: In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints is generated. Feasibility of the set of layout constraints is checked, which then is provided to a Linear Program solver for generating an output circuit layout.

Abstract: A method (and system) of automatically legalizing a circuit layout with layout objects in a presence of a plurality of non-uniform grids is disclosed. The method comprises generating a set of layout constraints comprising design rule constraints and gridding requirements based on the plurality of non-uniform grids. In addition, the method comprises processing the set of layout constraints to a feasible form using Boolean variables by determining infeasibility of the set of layout constraints, identifying infeasible layout constraints from the set of layout constraints, and resolving the infeasibility by a constraint relaxation process. Additionally, the method comprises generating an output circuit layout, for display to a user, by solving the set of layout constraints in the feasible form with standard linear program solvers.

Abstract: A method (and system) of automatically legalizing a circuit layout with layout objects in a presence of a plurality of non-uniform grids is disclosed. The method comprises generating a set of layout constraints comprising design rule constraints and gridding requirements based on the plurality of non-uniform grids. In addition, the method comprises processing the set of layout constraints to a feasible form using Boolean variables by determining infeasibility of the set of layout constraints, identifying infeasible layout constraints from the set of layout constraints, and resolving the infeasibility by a constraint relaxation process. Additionally, the method comprises generating an output circuit layout, for display to a user, by solving the set of layout constraints in the feasible form with standard linear program solvers.

Abstract: A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Abstract: In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints is generated. Feasibility of the set of layout constraints is checked, which then is provided to a Linear Program solver for generating an output circuit layout.

Abstract: A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.