Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: A semiconductor package includes a substrate having first and second surfaces, first and second pads disposed on the first and second surfaces respectively and electrically connected to each other, a semiconductor chip disposed on the first surface and connected to the first pads, a dummy chip disposed on the first surface, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate, an underfill between the semiconductor chip and the first surface of the substrate with an extension portion extended along facing side surfaces of the semiconductor chip and the dummy chip in the perpendicular direction, an upper end of the extension portion lower than the upper surface of the semiconductor chip, and a sealing material on the first surface to seal the semiconductor chip and the dummy chip.

Abstract: A semiconductor package includes a substrate having first and second surfaces, first and second pads disposed on the first and second surfaces respectively and electrically connected to each other, a semiconductor chip disposed on the first surface and connected to the first pads, a dummy chip disposed on the first surface, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate, an underfill between the semiconductor chip and the first surface of the substrate with an extension portion extended along facing side surfaces of the semiconductor chip and the dummy chip in the perpendicular direction, an upper end of the extension portion lower than the upper surface of the semiconductor chip, and a sealing material on the first surface to seal the semiconductor chip and the dummy chip.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.