Patents by Inventor Sucheta Nallamothu
Sucheta Nallamothu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7915164Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: GrantFiled: October 4, 2010Date of Patent: March 29, 2011Assignee: SanDisk 3D LLCInventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Patent number: 7915163Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: GrantFiled: June 22, 2009Date of Patent: March 29, 2011Assignee: SanDisk 3D LLCInventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Publication number: 20110021019Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: ApplicationFiled: October 4, 2010Publication date: January 27, 2011Inventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Publication number: 20090258462Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: ApplicationFiled: June 22, 2009Publication date: October 15, 2009Inventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar
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Patent number: 7566974Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: GrantFiled: September 29, 2004Date of Patent: July 28, 2009Assignee: SanDisk 3D, LLCInventors: Michael W. Konevecki, Usha Raghuram, Maitreyee Mahajani, Tanmay Kumar, Sucheta Nallamothu, Andrew J. Walker
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Patent number: 7508714Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: GrantFiled: May 21, 2007Date of Patent: March 24, 2009Assignee: SanDisk 3D LLCInventors: Luca G. Fasoli, Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker
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Patent number: 7505321Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.Type: GrantFiled: December 31, 2002Date of Patent: March 17, 2009Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Christopher Petti, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov
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Patent number: 7433233Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: GrantFiled: June 18, 2007Date of Patent: October 7, 2008Assignee: SanDisk 3D LLCInventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
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Patent number: 7432141Abstract: A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.Type: GrantFiled: September 8, 2004Date of Patent: October 7, 2008Assignee: SanDisk 3D LLCInventors: Shuo Gu, Sucheta Nallamothu
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Publication number: 20070242511Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: ApplicationFiled: June 18, 2007Publication date: October 18, 2007Inventors: En-Hsing Chen, Andrew Walker, Roy Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli
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Publication number: 20070217263Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: ApplicationFiled: May 21, 2007Publication date: September 20, 2007Inventors: Luca Fasoli, Roy Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew Walker
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Patent number: 7233522Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: GrantFiled: December 5, 2003Date of Patent: June 19, 2007Assignee: SanDisk 3D LLCInventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
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Patent number: 7221588Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: GrantFiled: December 5, 2003Date of Patent: May 22, 2007Assignee: Sandisk 3D LLCInventors: Luca G. Fasoli, Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker
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Publication number: 20060071074Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.Type: ApplicationFiled: September 29, 2004Publication date: April 6, 2006Applicant: Matrix Semiconductor, Inc.Inventors: Michael Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Andrew Walker, Tanmay Kumar
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Patent number: 7023739Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: GrantFiled: December 5, 2003Date of Patent: April 4, 2006Assignee: Matrix Semiconductor, Inc.Inventors: En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca G. Fasoli
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Publication number: 20060051911Abstract: A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.Type: ApplicationFiled: September 8, 2004Publication date: March 9, 2006Applicant: Matrix Semiconductor, Inc.Inventors: Shuo Gu, Sucheta Nallamothu
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Patent number: 7005350Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.Type: GrantFiled: December 31, 2002Date of Patent: February 28, 2006Assignee: Matrix Semiconductor, Inc.Inventors: Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Roy E. Scheuerlein, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov, Christopher Petti
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Patent number: 6960794Abstract: A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.Type: GrantFiled: December 31, 2002Date of Patent: November 1, 2005Assignee: Matrix Semiconductor, Inc.Inventors: Andrew J. Walker, S. Brad Herner, Maitreyee Mahajani, En-Hsing Chen, Roy E. Scheuerlein, Sucheta Nallamothu, Mark Clark
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Publication number: 20050128807Abstract: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.Type: ApplicationFiled: December 5, 2003Publication date: June 16, 2005Inventors: En-Hsing Chen, Andrew Walker, Roy Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli, James Cleeves
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Publication number: 20050122779Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Inventors: Luca Fasoli, Roy Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew Walker