Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements.

Abstract: A method and apparatus for automatically configuring circuit cards used in a computer system. The present invention includes a method and apparatus that enables the circuit cards to be automatically configured during system boot up without any user intervention. The present invention also includes a method for the computer system software to detect resources requested by the circuit cards in order to resolve any system resource conflicts.

Abstract: A method and apparatus for automatically configuring circuit cards used in a computer system. The present invention includes a method and apparatus that enables the circuit cards to be automatically configured during system boot up without any user intervention. The present invention also includes a method for the computer system software to detect resources requested by the circuit cards in order to resolve any system resource conflicts.

Abstract: A system for managing power consumption in a personal computer, specifically the CPU and on-board system devices. The present invention manages the power consumption of the CPU and on-board system devices (i.e., core logic) using a global event messaging scheme and an OS-Idle power event and interrupts to provide CPU power management. The CPU's low-power state is implemented such that any or a set of predetermined device interrupts will transition the CPU from low-power state to normal operation which commences at the first instruction of the interrupt handler invoked by the device interrupt. The power consumed by the platform/chipset and controller logic devices, i.e., core logic, influenced by system clocks can be managed by decreasing frequency or stopping the distributed clock(s) altogether when in low-power state.

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals.

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements.