Abstract: An exemplary radio fingerprint-based indoor localization method and system is disclosed that is resistant to spoofing or jamming attacks (e.g., at nearby radios, e.g., access points), among other types of interference. The exemplary method and system may be applied in the configuring of a secured convolutional neural network (S-CNNLOC) or secured deep neural network configured for attack-resistant fingerprint-based indoor localization.

Abstract: A snooping invalidation module is implemented at the network interface for a given core, or processing element, of a multicore or manycore device, e.g., NoC device, to discard packets with invalid header flits (e.g., duplicate packets) from being injected into the device, e.g., by a malicious hardware trojan implemented in the network interface. In some embodiments, a data-snooping detection circuit is implemented to detect a source of an on-going attack.

Abstract: The exemplified methods and systems provide hardware-circuit-level encryption for inter-core communication of photonic communication devices such as photonic network-on-chip devices. In some embodiments, the hardware-circuit level encryption uses authentication signatures that are based on process variation that inherently occur during the fabrication of the photonic communication device. The hardware level encryption can facilitate high bandwidth on-chip data transfers while preventing hardware-based trojans embedded in components of the photonic communication device such as PNoC devices or preventing external snooping devices from snooping data from the neighboring photonic signal transmission medium in a shared photonic signal transmission medium. In some embodiments, the hardware-circuit-level encryption is used for unicast/multicast traffic.

Abstract: An exemplary radio fingerprint-based indoor localization method and system is disclosed that is resistant to spoofing or jamming attacks (e.g., at nearby radios, e.g., access points), among other types of interference. The exemplary method and system may be applied in the configuring of a secured convolutional neural network (S-CNNLOC) or secured deep neural network configured for attack-resistant fingerprint-based indoor localization.

Abstract: A snooping invalidation module is implemented at the network interface for a given core, or processing element, of a multicore or manycore device, e.g., NoC device, to discard packets with invalid header flits (e.g., duplicate packets) from being injected into the device, e.g., by a malicious hardware trojan implemented in the network interface. In some embodiments, a data-snooping detection circuit is implemented to detect a source of an on-going attack.

Abstract: The exemplified methods and systems provide hardware-circuit-level encryption for inter-core communication of photonic communication devices such as photonic network-on-chip devices. In some embodiments, the hardware-circuit level encryption uses authentication signatures that are based on process variation that inherently occur during the fabrication of the photonic communication device. The hardware level encryption can facilitate high bandwidth on-chip data transfers while preventing hardware-based trojans embedded in components of the photonic communication device such as PNoC devices or preventing external snooping devices from snooping data from the neighboring photonic signal transmission medium in a shared photonic signal transmission medium. In some embodiments, the hardware-circuit-level encryption is used for unicast/multicast traffic.

Abstract: A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model.

Abstract: A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model.