Patents by Inventor Sudharshan Sugavanesh Udhayakumar

Sudharshan Sugavanesh Udhayakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121931
    Abstract: Methods and structures for providing thermal dissipating elements on integrated circuit (“IC”) dies are disclosed. A thermal dissipating element placement assembly, such as a pin fin placement assembly, along with a vacuum pickup assembly, can be used to assist with simultaneous placement of multiple pin fins with desired profiles on desired locations of the IC die. The pin fin placement assembly may be comprised of one or more plates with a plurality of apertures therein for receiving the pin fins. The pin fin placement assembly can be further incorporated into a thermal cooling structure, which can include a manifold configured to encase the IC die and attached pin fins.
    Type: Application
    Filed: July 25, 2023
    Publication date: April 11, 2024
    Inventors: Yingshi Tang, Yingying Wang, Padam Jain, Emad Samadiani, Sudharshan Sugavanesh Udhayakumar, Madhusudan K. Iyengar
  • Patent number: 11955406
    Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 9, 2024
    Assignee: Google LLC
    Inventors: Yingying Wang, Emad Samadiani, Madhusudan K. Iyengar, Padam Jain, Xiaojin Wei, Teckgyu Kang, Sudharshan Sugavanesh Udhayakumar, Yingshi Tang
  • Publication number: 20240055317
    Abstract: A compliant pad spacer utilized in a three-dimensional IC packaging is provided. The compliant pad spacer may be utilized to provide adequate support among the substrates or boards, such as packing substrates, interposers or print circuit broads (PCBs), so as to minimize the effects of substrate warpage or structural collapse in the IC packaging. In one example, the compliant pad spacer includes an insulating material, such as silicon-based polymer composites having ceramic fillers disposed therein.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Inventors: Emad Samadiani, Padam Jain, Yingshi Tang, Sue Yun Teng, Nicholas Chao Wei Wong, Kieran Miller, Sudharshan Sugavanesh Udhayakumar
  • Publication number: 20240038620
    Abstract: A pin fin placement assembly utilized to form pin fins in a thermal dissipating feature is provided. The pin fin placement assembly may place the pin fins on an IC die disposed in the IC package. The pin fin placement assembly may assist massively placing the pin fins with desired profiles and numbers on desired locations of the IC die. The plurality of pin fins is formed in a first plurality of apertures in the pin fin placement assembly. A thermal process is then performed to solder the plurality of pin fins on the IC die.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicants: Google LLC, Google LLC
    Inventors: Yingshi Tang, Yingying Wang, Padam Jain, Emad Samadiani, Sudharshan Sugavanesh Udhayakumar, Madhusudan K. Iyengar