Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: Electrostatic discharge (ESD) protection devices with high current capability are described. The ESD protection device may include a pair of bidirectional diodes (first and second bidirectional diodes) connected in series. Each of the bidirectional diodes includes a low capacitance (LC) diode and a bypass diode connected in parallel. During ESD events, current flows through the LC diode of the first bidirectional diode and the bypass diode of the second bidirectional diode. Particular arrangements of the LC diodes and the bypass diodes are devised to facilitate uniform distribution of the current throughout an area occupied by the ESD protection device.

Abstract: Semiconductor devices with high current capability for ESD or surge protection are described. The semiconductor device includes multiple n-type semiconductor regions in a p-type semiconductor layer. Each of the n-type semiconductor regions may have a footprint with a circular, oval, or obround shape. Moreover, a boundary of the footprint may be spaced apart from an isolation structure that surrounds the p-type semiconductor layer. The n-type semiconductor regions may be coupled to a terminal through individual groups of contacts that are connected to the n-type semiconductor regions, respectively. Additionally, or alternatively, the p-type semiconductor layer surrounded by the isolation structure may not include any re-entrant corner.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: A system includes: 1) a buffer circuit; 2) circuitry coupled to an input of the buffer circuit; 3) a load coupled to an output of the buffer circuit; and 4) a clamp circuit coupled between an input of the buffer circuit and the output of the buffer circuit. The clamp circuit includes: 1) a bipolar junction transistor (BJT); 2) a first resistor with a first end coupled to a base terminal of the BJT and with a second end coupled to a collector terminal of the BJT; and 3) a second resistor with a first end coupled to the collector terminal of the BJT and with a second end coupled to the input of the buffer circuit. The second resistor is between an output of the circuitry and the input of the buffer circuit.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Abstract: A detection circuit includes a first transistor coupled to a gate of a high power transistor, a second transistor whose source is coupled to a drain of the first transistor, a first voltage divider coupled to a source of the first transistor, and a second voltage divider coupled to the source of the second transistor. The first transistor is configured to generate a first transistor output voltage representative of a gate voltage of the high power transistor shifted based on a first gate-to-source voltage of the first transistor. The second transistor is configured to generate a second gate-to-source voltage substantially equal to the first gate-to-source voltage. The first divider is configured to divide the first transistor output voltage by a first factor. The second divider is configured to divide the second gate-to-source voltage by a second factor correlated with the first factor.

Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

Abstract: One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage.

Abstract: One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage.

Abstract: A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.