Patents by Inventor Sudipto Chakraborty

Sudipto Chakraborty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210194427
    Abstract: A remotely powered low power oscillator. According to an embodiment of the present invention, a method comprises an oscillator core, in a first environment, generating an oscillating signal; a power management system, in a second environment, supplying power to the oscillator core to operate the oscillator core; a sensing system, in the first environment, sensing one or more parameters of the oscillator core, and generating one or more signals representing said one or more parameters; transmitting the one or more signals from the sensing system to the second environment; and using the one or more signals in the second environment to control the power supplied to the oscillator core from the power management system.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210175407
    Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Steven J. Holmes, Bruce B. Doris, Matthias Georg Gottwald, Rajiv Joshi, Sudipto Chakraborty
  • Publication number: 20210174858
    Abstract: A structure of a memory device is described. The structure can include an array of memory cells. A memory cell can include at least one metal-oxide-semiconductor (MOS) element, where a source terminal of the at least one MOS element is connected to a drain terminal of the MOS element. The source terminal being connected to the drain terminal can cause the at least one MOS element to exhibit capacitive behavior for storing electrical energy. A first transistor can be connected to the at least one MOS element, where an activation of the first transistor can facilitate a write operation to the memory cell. A second transistor can be connected to the at least one MOS element, where an activation of the second transistor can facilitate a read operation from the memory cell.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 10, 2021
    Inventors: Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11025234
    Abstract: Methods and systems for regulating supply voltage is described. In an example, a device can receive unregulated supply. The device can be connected to a ring oscillator and an integrated circuit. The device can be configured to regulate the unregulated supply to a first voltage. The device can be further configured to provide the regulated supply to the ring oscillator, where the ring oscillator operates with the regulated supply. The device can be further configured to, in response to a change in the regulated supply from the first voltage to a second voltage, adjust the changed regulated supply to return to the first voltage to cause the ring oscillator to operate with a constant regulated supply having the first voltage.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11024354
    Abstract: Circuits and methods are disclosed that, in embodiments, may be used for low power memory signal readout. In an embodiment, the circuit comprises a front end stage including an impedance conversion network for receiving a signal and providing voltage or current gain, and a wideband multiplier for receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; and a baseband stage including a voltage mode mixer for receiving the differential output signals from the wideband multiplier and providing voltage gain, and a bandpass filter/amplifier for receiving a mixer output signal from the voltage mode mixer and filtering and amplifying the mixer output signal; and wherein DC voltages of the front-end stage are biased independently of a biasing of DC voltages of the baseband stage.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210151848
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 10977018
    Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: L. James Hwang, Michael Gill, Tom Shui, Jorge E. Carrillo, Alfred Huang, Sudipto Chakraborty
  • Patent number: 10958248
    Abstract: A method and apparatus are described to implement a bandpass filter in a current mode logic (CML) stage of a clock tree in an electronic system. The bandpass filter has a bandpass filter transfer function to attenuate frequencies lower than and higher than a carrier frequency. The bandpass filter uses adjustable active inductors and capacitive source degeneration. Adjustable resistors may be controlled to move a peak frequency of the bandpass filter transfer function to a higher or lower frequency. The adjustable active inductors and capacitive degeneration may consist of field effect transistors.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yang You, Glen A. Wiedemeier, Chad Andrew Marquart, Jeffrey Kwabena Okyere, Daniel M. Dreps, Sudipto Chakraborty
  • Publication number: 20210050829
    Abstract: An analog front-end (AFE) circuit for conditioning a sensor signal is disclosed. The AFE circuit includes a first stage configured to amplify and filter the sensor signal. The first stage comprises a biquadratic filter comprising a first plurality of DC-coupled transconductance amplifiers. The AFE further includes a second stage configured to further amplify and filter the amplified sensor signal, and to compensate a direct current (DC) offset of the first stage. The second stage comprises a second plurality of AC-coupled transconductance amplifiers. Each transconductance amplifier of the first plurality and of the second plurality has a programmable transconductance and comprises a plurality of subthreshold-biased transistors.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 10903544
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210013833
    Abstract: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventor: Sudipto Chakraborty
  • Patent number: 10879923
    Abstract: Methods and systems to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a current mode digital-to-analog converter (DAC) configured to multiply an input signal with an input current to generate a signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the signal into at least a first current having a first amplitude and a second current having a second amplitude. The device can further include a mixer configured to multiply the second current with a clock signal to generate a third current. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 10856225
    Abstract: A system of multiple concurrent receivers is described to process multiple narrow bandwidth wireless signals with arbitrary bandwidth and center frequency separation. These multiple receivers may provide a downconverted signal at the baseband frequency to process signal bandwidth using the lowest power consumption while using fully modular signal processing blocks operating at the low frequency. The concurrent receivers may operate from a single high frequency amplifier and may be derived from a low impedance point to reduce loading and improve scalability. The center frequency and bandwidth of each of the channels as well as phases of each of the channels may be independently reconfigured to achieve scalability, and on-chip test and calibration capability.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 1, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sudipto Chakraborty, Ram Pratap Aditham
  • Patent number: 10833685
    Abstract: A voltage controlled oscillator (VCO) circuit and method achieves linearized frequency tuning over an extended range of analog tuning voltage by implementing a magnetic balun/transformer for biasing and coupling varactor elements. An active negative transconductance circuit of cross-coupled transistors have drains connected with a resonant tank circuit and at least a first varactor element having ends connected to respective first ends of respective first coils of a respective first and second magnetic balun. Respective second ends of respective first coils of respective first and second baluns are connected to a first reference supply voltage. A second varactor element has ends connecting respective first ends of respective second coils of said first and second baluns. A sinking of a bias current through the resonant tank circuit and the transconductance circuit generates an oscillating signal. A calibration method achieves precise VCO gain over wide tuning voltage range, thereby enhancing VCO linearity.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20200343614
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 10797646
    Abstract: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 6, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudipto Chakraborty
  • Publication number: 20200204167
    Abstract: In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Inventor: Sudipto Chakraborty
  • Publication number: 20200153465
    Abstract: A wireless wake-up receiver includes multiple signal chains each signal chain being coupled to continuously receive a signal from a respective antenna and to provide a respective detected pattern at a signal chain output. Each signal chain includes a first path having a mixer-first architecture and operates in a bandpass-mode using differential signals. The wireless wake-up receiver also includes a digital correlator operable to receive the respective detected patterns and to determine whether one of the respective detected patterns is equal to a desired pattern.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Sudipto Chakraborty, Jens Graul, Ram Pratap Aditham
  • Patent number: 10646832
    Abstract: The present invention discloses high selectivity copolyimide membranes for gas, vapor, and liquid separations. Gas permeation tests on these copolyimide membranes demonstrated that they not only showed high selectivity for CO2/CH4 separation, but also showed extremely high selectivities for H2/CH4 and He/CH4 separations. These copolyimide membranes can be used for a wide range of gas, vapor, and liquid separations such as separations of CO2/CH4, He/CH4, CO2/N2, olefin/paraffin separations (e.g. propylene/propane separation), H2/CH4, He/CH4, O2/N2, iso/normal paraffins, polar molecules such as H2O, H2S, and NH3 mixtures with CH4, N2, H2. The high selectivity copolyimide membranes have UV cross-linkable sulfonyl functional groups and can be used for the preparation of UV cross-linked high selectivity copolyimide membranes with enhanced selectivities. The invention also includes blend polymer membranes comprising the high selectivity copolyimide and polyethersulfone.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 12, 2020
    Inventors: Chunqing Liu, Sudipto Chakraborty, Nicole Karns
  • Publication number: 20200112286
    Abstract: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventor: Sudipto Chakraborty