Patents by Inventor Sudipto Ranendra Roy
Sudipto Ranendra Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6987321Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: GrantFiled: November 21, 2003Date of Patent: January 17, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Publication number: 20050112799Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: November 15, 2004Publication date: May 26, 2005Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu
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Patent number: 6821888Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: GrantFiled: February 13, 2002Date of Patent: November 23, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Publication number: 20040227247Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: ApplicationFiled: November 21, 2003Publication date: November 18, 2004Applicant: CHARTERED SEMICONDUCTOR MANFACTURING LTD.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6813796Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: GrantFiled: February 3, 2003Date of Patent: November 9, 2004Assignee: Chartered SemiconductorInventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6720204Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.Type: GrantFiled: April 11, 2002Date of Patent: April 13, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6705512Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.Type: GrantFiled: March 15, 2002Date of Patent: March 16, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Patent number: 6692579Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.Type: GrantFiled: January 19, 2001Date of Patent: February 17, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
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Patent number: 6683002Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: GrantFiled: August 10, 2000Date of Patent: January 27, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6670209Abstract: A process for forming a planarized metal layer by forming the plug and overlying metal interconnect simultaneously in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device is described. Semiconductor device structures in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A trench is patterned into the insulating layer and a via opening is made within the trench through the insulating layer to one of the underlying semiconductor device structures. A metal layer is deposited overlying the insulating layer and within the trench and via opening. The metal layer overlying insulating layer is polished away leaving the metal layer within the trench to form a metal pixel and within the via opening to form an interconnect between the metal pixel and the underlying semiconductor device wherein the top surface of the substrate is planarized.Type: GrantFiled: September 11, 1998Date of Patent: December 30, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Sudipto Ranendra Roy
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Publication number: 20030192943Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.Type: ApplicationFiled: April 11, 2002Publication date: October 16, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Publication number: 20030140943Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: ApplicationFiled: February 3, 2003Publication date: July 31, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6547652Abstract: An apparatus for multiple component slurry distribution during semiconductor wafer polishing operations. Concurrent polishing pad conditioning is obtained by means of a novel polishing pad design where polishing pads are mounted in a cylindrical configuration as opposed to the conventional flat surface configuration. A polishing pad conditioner is provided to refurbish the polishing pad.Type: GrantFiled: November 22, 2000Date of Patent: April 15, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Sudipto Ranendra Roy
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Patent number: 6540841Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: GrantFiled: June 30, 2000Date of Patent: April 1, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6521079Abstract: An apparatus for closed loop slurry distribution during semiconductor wafer polishing operations. The traditional peristaltic pump for slurry supply is eliminated thus eliminating irregularities in the conventional slurry supply. Common platform mounting of the slurry reservoir and the polishing apparatus resulting in concurrent and identical motion of the slurry supply reservoir and the polishing apparatus. The polishing medium is mounted on the outside of a cylinder as opposed to the conventional table mounting, the polishing medium rotates around the axis of the cylinder on which this polishing medium is mounted. The polishing pads are in direct physical contact with the slurry supply without the intervention of any slurry pumping arrangement.Type: GrantFiled: October 6, 2000Date of Patent: February 18, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Sudipto Ranendra Roy
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Publication number: 20030032275Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: February 13, 2002Publication date: February 13, 2003Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Patent number: 6475810Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.Type: GrantFiled: August 10, 2000Date of Patent: November 5, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu, Simon Chooi, Yakub Aliyu
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Patent number: 6429117Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.Type: GrantFiled: July 19, 2000Date of Patent: August 6, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: John Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Publication number: 20020100794Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.Type: ApplicationFiled: March 15, 2002Publication date: August 1, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Publication number: 20020096190Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.Type: ApplicationFiled: January 19, 2001Publication date: July 25, 2002Applicant: Chartered Semiconductor Manufacturing Inc.Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta