Patents by Inventor Suebphong Yenrudee

Suebphong Yenrudee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734247
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 4, 2020
    Assignee: UTAC Headquarters PTE. LTD
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 10600741
    Abstract: Methods of manufacturing semiconductor packages with metal-plated shields include roughening surfaces of a molding compound by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. In one embodiment, the method includes obtaining a molded array including a plurality of dies coupled to a substrate and a molding compound encapsulating the plurality of dies, coating all exposed surfaces of the molding compound with an adhesion promoter material, heating the molded array with an adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film, and etching away the baked film, resulting in the molding compound having the roughened surfaces. Preferably, the method also includes depositing a catalyst material on the roughened surfaces before a metal layer is coated on the roughened surfaces to speed up the time for the metal layer to adhere to the roughened surfaces.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 24, 2020
    Assignee: Utac Headquarters PTE. LTD.
    Inventors: Suebphong Yenrudee, Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul
  • Patent number: 10361146
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 23, 2019
    Assignee: UTAC Headquarters PTE, LTD.
    Inventors: Saravuth Sirinorakul, Keith M. Edwards, Suebphong Yenrudee, Albert Loh
  • Patent number: 10325782
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 18, 2019
    Assignee: UTAC Headquarters PTE. Ltd.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Publication number: 20190181077
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
    Type: Application
    Filed: January 9, 2019
    Publication date: June 13, 2019
    Applicant: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Keith M. Edwards, Suebphong Yenrudee, Albert Loh
  • Patent number: 10276477
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 30, 2019
    Assignee: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Keith M. Edwards, Suebphong Yenrudee, Albert Loh
  • Patent number: 10269686
    Abstract: Embodiments of the present invention relate to a semiconductor package that includes a locking feature. The locking feature is provided by an unnatural surface roughness of a first molding compound to increase adhesion with a second molding compound. Surfaces of first molding compound are roughened by an abrasion process such that the surfaces are rougher than a natural surface roughness. The roughened surfaces of the first molding compound provide better adhesion of the second molding compound to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness).
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 23, 2019
    Assignee: UTAC Headquarters PTE, LTD.
    Inventors: Suebphong Yenrudee, Saravuth Sirinorakul
  • Patent number: 10242953
    Abstract: Embodiments of the present invention relate to a semiconductor package with a metal-plated shield. Surfaces of molding compound are roughened by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. The roughened surfaces provide better adhesion of the metal-plated shield to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness). A catalyst material can be deposited on the roughened surfaces of the molding compound before a metal layer is coated on the roughened surfaces of the molding compound to speed up the time for the metal layer to adhere to the roughened surfaces of the molding compound. The metal-plated shield can include plurality of metal layers plated on top of each other.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: March 26, 2019
    Assignee: Utac Headquarters PTE. Ltd
    Inventors: Suebphong Yenrudee, Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul
  • Patent number: 10163658
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 25, 2018
    Assignee: UTAC HEADQUARTERS PTE, LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 10096490
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 9, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 10032645
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is fondled from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: July 24, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 9922843
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: March 20, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 9917038
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: March 13, 2018
    Assignee: UTAC HEADQUARTERS PTE LTD
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Publication number: 20180061667
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 1, 2018
    Applicant: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Publication number: 20170352554
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.
    Type: Application
    Filed: August 2, 2017
    Publication date: December 7, 2017
    Applicant: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Publication number: 20170352610
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Application
    Filed: August 9, 2017
    Publication date: December 7, 2017
    Applicant: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Publication number: 20170352555
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Application
    Filed: August 10, 2017
    Publication date: December 7, 2017
    Applicant: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 9805955
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 31, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 9449900
    Abstract: A support feature on a leadframe to support a semiconductor die during placement of the die on the leadframe and minimize the collapsing effect of the connector bumps of the die after reflowing. In some embodiments, the support features are formed from material that is different from the leadframe, such as by a ball drop process or a plating process. In some embodiments, the support features are formed from the leadframe material, such as by etching. In some embodiments, the support features are covered with a coating material.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: September 20, 2016
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 9029198
    Abstract: A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 12, 2015
    Assignee: UTAC Thai Limited
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee