Abstract: A control unit controls execution of an instruction according to a decode result of an instruction code. A GRA register stores an access attribute for each of the plurality of general-purpose registers. A mode storage unit stores modes for controlling an operation of a CPU. When the control unit makes a request for access to the general-purpose register, register access allowance determining circuit determines whether the access to the general-purpose register in question is to be allowed or not, depending on the access attribute stored in the GRA register and the mode stored in the mode storage unit. Therefore, the number of the general-purpose registers used corresponding to the mode can be changed, and efficiency of use of the general-purpose registers can be optimized.

Abstract: A semiconductor device includes first and second central processing units (0, 3) and a set of monitoring registers (60) provided inside or outside the second central processing unit (3). Information representing an internal state of the first central processing unit (0) is transferred from the first central processing unit (0) to the set of monitoring registers (60) during execution of a program, and the set of monitoring registers (60) holds such transferred information. The set of monitoring registers (60) is mapped in a memory space of the second central processing unit (3).

Abstract: A control unit controls execution of an instruction according to a decode result of an instruction code. A GRA register stores an access attribute for each of the plurality of general-purpose registers. A mode storage unit stores modes for controlling an operation of a CPU. When the control unit makes a request for access to the general-purpose register, register access allowance determining circuit determines whether the access to the general-purpose register in question is to be allowed or not, depending on the access attribute stored in the GRA register and the mode stored in the mode storage unit. Therefore, the number of the general-purpose registers used corresponding to the mode can be changed, and efficiency of use of the general-purpose registers can be optimized.

Abstract: A data processing device comprises an instruction decoding unit for decoding a code of either a division instruction or a remainder instruction applied thereto, the instruction code having a size field for storing data size information. When a control unit receives a decoded result from the instruction decoding unit, the decoded result indicating the data size information stored in the size field of the instruction code, it presets a number of times that one loop iteration comprised of steps required for executing either the division instruction or the remainder instruction is to be carried out, based on the data size information. An ALU disposed within an arithmetic unit performs the loop iteration for either the division instruction or the remainder instruction only the number of times preset by the control unit.

Abstract: Exemplary embodiments of the present invention are directed toward a technique which facilitates the process instruction codes in processor. According to the present invention, a memory device is provided which comprises a plurality of 2N-bit word boundaries, where N is greater than or equal to one. The processor of the present invention executes instruction codes of a 2N-bit length and a N-bit length. The instruction codes are stored in the memory device is such a way that the 2-N bit word boundaries contains either a single 2N-bit instruction code or two N-bit instruction codes. The most significant bit of each instruction code serves as a instruction format identifier which controls the execution (or decoding) sequence of the instruction codes. As a result, only two transfer paths from an instruction fetch portion to an instruction decode portion of the processor are necessary thereby reducing the hardware requirement of the processor and increasing system throughput.

Abstract: For a processor having instruction codes of two instruction lengths (16 bits and 32 bits), methods of locating the instruction codes are limited to two types: (1) two 16-bit instruction codes are stored within 32-bit word boundaries, and (2) a single 32-bit instruction code is stored intactly within the 32-bit word boundaries. A branch destination address is specified only on the 32-bit word boundary. The MSB of each instruction code serves as a 1-bit instruction length identifier for controlling the execution sequence of the instruction codes. This provides two transfer paths from an instruction fetch portion to an instruction decode portion within the processor, achieving reduction in code side and in the amount of hardware and, accordingly, the increase in operating speed.