Patents by Inventor Suguru SAITO
Suguru SAITO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170507Abstract: There is provided an imaging device capable of reducing dark current and white spots, and a manufacturing method for the imaging device. An imaging device includes a first semiconductor substrate, a plurality of sensor pixels that is provided on the first semiconductor substrate and performs photoelectric conversion, and a trench provided in a depth direction of the first semiconductor substrate from a first main surface of the first semiconductor substrate. The first semiconductor substrate is a (110) substrate in which the first main surface is a (110) plane. At least a part of a side surface of the trench is a (111) plane.Type: ApplicationFiled: March 4, 2022Publication date: May 23, 2024Inventors: JUN YOSHIGIWA, TOMOKI HIRANO, SUGURU SAITO, RIKIICHI OONO
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Patent number: 11990366Abstract: Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.Type: GrantFiled: February 1, 2022Date of Patent: May 21, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Suguru Saito, Nobutoshi Fujii, Masaki Haneda, Kazunori Nagahata
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Publication number: 20240047503Abstract: Provided are a semiconductor device capable of lowering the temperature of the entire joining process to room temperature, a method for manufacturing a semiconductor device, and an electronic device. The semiconductor device includes: a first insulating film; a plurality of first joining electrodes formed on a surface of the first insulating film; a second insulating film; a plurality of second joining electrodes formed on a surface of the second insulating film; and a metal film covering an entire surface of a joining surface including the first insulating film and the plurality of first joining electrodes and an entire surface of a joining surface including the second insulating film and the plurality of second joining electrodes. The first insulating film includes a first dug portion that is formed between at least some joining electrodes of the plurality of first joining electrodes and separating the metal film between the joining electrodes.Type: ApplicationFiled: October 29, 2021Publication date: February 8, 2024Inventors: SUGURU SAITO, NOBUTOSHI FUJII
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Publication number: 20240006437Abstract: While improving the bonding strength between a plurality of semiconductor substrates, the passage of noise from one of the plurality of semiconductor substrates to another is suppressed.Type: ApplicationFiled: November 8, 2021Publication date: January 4, 2024Inventors: YOSUKE NITTA, NOBUTOSHI FUJII, SUGURU SAITO
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Publication number: 20240006448Abstract: Provided is an imaging device including: a first semiconductor substrate provided with a photoelectric conversion element, a second semiconductor substrate stacked on the first semiconductor substrate with an interlayer insulating film interposed therebetween and provided with a pixel circuit that reads out charges generated in the photoelectric conversion element as a pixel signal, and a via that penetrates the interlayer insulating film and electrically connects a first surface of the first semiconductor substrate facing the second semiconductor substrate and at least a part of a second surface of the second semiconductor substrate facing the first surface.Type: ApplicationFiled: October 11, 2021Publication date: January 4, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takeya MOCHIZUKI, Keiichi NAKAZAWA, Shinichi YOSHIDA, Kenya NISHIO, Nobutoshi FUJII, Suguru SAITO, Masaki OKAMOTO, Ryosuke KAMATANI, Yuichi YAMAMOTO, Kazutaka IZUKASHI, Yuki MIYANAMI, Hirotaka YOSHIOKA, Hiroshi HORIKOSHI, Takuya KUROTORI, Shunsuke FURUSE, Takayoshi HONDA
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Patent number: 11862662Abstract: Provided is an imaging device (1) including: an imaging element (10); and a semiconductor element (20, 30) provided to be opposed to the imaging element and electrically coupled to the imaging element. The semiconductor element includes: a wiring region (20A, 30A) provided in a middle portion and a peripheral region (20B, 30B) outside the wiring region; a wiring layer (22, 32) having a wiring line in the wiring region; a semiconductor substrate (21, 31) opposed to the imaging element with the wiring layer interposed therebetween and having a first surface (Sa, Sc) and a second surface (Sb, Sd) in order from a side of the wiring layer; and a polishing adjustment section (23, 33) including a material that is lower in polishing rate than a constituent material of the semiconductor substrate, the polishing adjustment section being disposed in at least a portion of the peripheral region and provided in a thickness direction of the semiconductor substrate from the second surface.Type: GrantFiled: October 9, 2019Date of Patent: January 2, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Sotetsu Saito, Suguru Saito, Nobutoshi Fujii
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Publication number: 20230304144Abstract: A film formation device having a high operation rate is provided. The film formation device includes: a film formation chamber (2) in which at least a film formation material (M) and a film formation target (S) are provided, wherein the film formation chamber (2) can be set to a predetermined film formation atmosphere; a hearth liner (23) provided inside the film formation chamber (2) to accommodate the film formation material (M); a heating source (24) provided inside the film formation chamber (2) to heat the film formation material (M) accommodated in the hearth liner (23); and a material supply chamber (3) having a material-filled unit (35) that is filled with the film formation material (M) to supply to the hearth liner (23). The material supply chamber (3) is connected to the film formation chamber (2) via a communication path (36) having a gate valve (37) and can be set to a predetermined pressure atmosphere.Type: ApplicationFiled: October 19, 2021Publication date: September 28, 2023Inventors: Makoto IGARASHI, Suguru SAITO, Yuya NONAKA
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Patent number: 11769784Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.Type: GrantFiled: April 8, 2022Date of Patent: September 26, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Suguru Saito, Nobutoshi Fujii
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Publication number: 20230282661Abstract: A contact of a glass substrate with an on-chip lens is suppressed while suppressing occurrence of flare. A package includes a flattening film covering an on-chip lens formed on a light incidence side of a substrate having an element formed thereon, a transparent substrate formed on the light incidence side of the flattening film, a hollow portion formed in a region overlapping the on-chip lens when seen in a plan view with respect to at least one of between the flattening film and the transparent substrate and inside the transparent substrate, and a through-hole making the hollow portion communicate with the outside.Type: ApplicationFiled: August 13, 2021Publication date: September 7, 2023Inventors: YOSUKE NITTA, NOBUTOSHI FUJII, SUGURU SAITO, YOICHI OOTSUKA
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Publication number: 20230268369Abstract: Provided is a semiconductor device with a wiring layer including a plurality of wiring lines extending in a first direction; a first insulating film stacked on the wiring layer that has a gap region between the plurality of wiring lines adjacent to each other in a second direction; and a second insulating film between the plurality of wiring lines and the first insulating film. Each wiring line includes a metal film and a barrier metal layer. The metal film includes an electrically conductive material including a first metal. The barrier metal layer partially covers surroundings of the metal film in a cross section orthogonal to the first direction and includes a material including a second metal. The second metal prevents diffusion of the first metal. The second insulating film includes an insulating material and covers a portion of the metal film. The insulating material prevents diffusion of the first metal.Type: ApplicationFiled: July 6, 2021Publication date: August 24, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Koichi SEJIMA, Takashi FUKATANI, Kenya NISHIO, Masaki HANEDA, Nobutoshi FUJII, Suguru SAITO
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Publication number: 20230261016Abstract: The present feature relates to a solid-state imaging device that allows generation of flare to be reduced and a manufacturing method therefor. A solid-state imaging device according to the present feature includes a semiconductor substrate having a pixel area having a plurality of pixels provided therein, and a transparent structure joined to a light incident surface side of the semiconductor substrate with resin and having a hollow structure. In the solid-state imaging device according to the present feature, the transparent structure includes a glass substrate and a transparent film, and the hollow structure is formed between the glass substrate and the transparent film. The present feature can be applied for example to imaging devices.Type: ApplicationFiled: June 25, 2021Publication date: August 17, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Nobutoshi FUJII, Suguru SAITO, Takashi FUKATANI
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Publication number: 20230223420Abstract: A first light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric converter that is provided as a layer common to the plurality of pixels, and contains a compound semiconductor material, and a first electrode layer that is provided between the plurality of pixels on light incident surface side of the photoelectric converter, and has a light-shielding property.Type: ApplicationFiled: January 18, 2023Publication date: July 13, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shuji MANDA, Ryosuke MATSUMOTO, Suguru SAITO, Shigehiro IKEHARA, Tetsuji YAMAGUCHI, Shunsuke MARUYAMA
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Publication number: 20230107566Abstract: Provided is an imaging unit more efficiently manufacturable with high dimensional precision. The imaging unit includes: a sensor board including an imaging device, in which the imaging device has a plurality of pixels and allows generation of a pixel signal by receiving outside light in each of the plurality of pixels; a bonding layer including an inorganic insulating material; and a circuit board including a circuit chip and an organic insulating layer, in which a circuit chip has a signal processing circuit that performs signal processing for the pixel signal and is bonded to the sensor board through the bonding layer, and the organic insulating layer covers a vicinity of the circuit chip.Type: ApplicationFiled: November 30, 2022Publication date: April 6, 2023Inventors: KENYA NISHIO, SUGURU SAITO
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Patent number: 11616093Abstract: A first light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric converter that is provided as a layer common to the plurality of pixels, and contains a compound semiconductor material, and a first electrode layer that is provided between the plurality of pixels on light incident surface side of the photoelectric converter, and has a light-shielding property.Type: GrantFiled: December 12, 2018Date of Patent: March 28, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shuji Manda, Ryosuke Matsumoto, Suguru Saito, Shigehiro Ikehara, Tetsuji Yamaguchi, Shunsuke Maruyama
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Publication number: 20230067340Abstract: There are provided a light emitting device capable of forming a light emitting element on a suitable substrate and a method of manufacturing the same. A light emitting device according to the present disclosure includes: a first substrate; a plurality of light emitting elements that are provided on a first surface of the first substrate; and a second substrate that is provided on a second surface of the first substrate opposite to the first surface.Type: ApplicationFiled: January 6, 2021Publication date: March 2, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Suguru SAITO, Yuichi YAMAMOTO, Nobutoshi FUJII, Taizo TAKACHI
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Patent number: 11543621Abstract: There is provided a camera module including a stacked lens structure including a plurality of lens substrates. The plurality of lens substrates includes a first lens substrate including a first lens that is disposed at an inner side of a through-hole formed in the first lens substrate, and a second lens substrate including a second lens that is disposed at an inner side of a through-hole formed in the second lens substrate, wherein the first lens substrate is directly bonded to the second lens substrate. The camera module further includes an electromagnetic drive unit configured to adjust a distance between the stacked lens structure and a light-receiving element.Type: GrantFiled: January 16, 2018Date of Patent: January 3, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Munekatsu Fukuyama, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Yusuke Moriya, Minoru Ishida
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Patent number: 11538843Abstract: Provided is an imaging unit more efficiently manufacturable with high dimensional precision. The imaging unit includes: a sensor board including an imaging device, in which the imaging device has a plurality of pixels and allows generation of a pixel signal by receiving outside light in each of the plurality of pixels; a bonding layer including an inorganic insulating material; and a circuit board including a circuit chip and an organic insulating layer, in which a circuit chip has a signal processing circuit that performs signal processing for the pixel signal and is bonded to the sensor board through the bonding layer, and the organic insulating layer covers a vicinity of the circuit chip.Type: GrantFiled: March 5, 2019Date of Patent: December 27, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kenya Nishio, Suguru Saito
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Patent number: 11525984Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like.Type: GrantFiled: October 26, 2021Date of Patent: December 13, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Yusuke Moriya, Masanori Iwasaki, Takashi Oinoue, Yoshiya Hagimoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
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Publication number: 20220375984Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.Type: ApplicationFiled: April 8, 2022Publication date: November 24, 2022Inventors: SUGURU SAITO, NOBUTOSHI FUJII
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Publication number: 20220359620Abstract: An imaging device according to an embodiment of the present disclosure includes: a first semiconductor substrate (100) provided with pixels including a photoelectric conversion element (PD) and floating diffusion (FD) that temporarily holds a charge output from the photoelectric conversion element (PD); and a semiconductor layer (200Y) provided on the first semiconductor substrate (100) via an insulating film (123), the semiconductor layer (200Y) including a readout circuit unit (539) that reads out the charge held in the floating diffusion (FD) and outputs a pixel signal, in which the semiconductor layer (200Y) is formed of an organic semiconductor material.Type: ApplicationFiled: June 17, 2020Publication date: November 10, 2022Inventors: KENYA NISHIO, SUGURU SAITO, NOBUTOSHI FUJII, HIROTAKA YOSHIOKA