Abstract: Dual mode T-switches driven by at least one low-impedance switch driver, to connect at least four wires of a multiwire bus to a multi-input comparator (MIC) of a plurality of MICs in a first mode of Orthogonal Vector Signaling operation, and in a full-duplex mode of operation, using the low-impedance switch driver to disable a corresponding subset of T-switches to selectively disconnect a pair of wires of the multiwire bus from the MIC while using low-impedance enable signal paths in the low-impedance switch drivers to shunt capacitively-coupled interfering outbound signals received at the MIC from the selectively disconnected pair of wires in the full-duplex mode of operation.

Abstract: A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme is disclosed. The multi-stage CTLE comprises a first stage transformer-based inductive peaking and a second stage resistive load. The first stage transformer-based inductive peaking is configured to control high frequency peaking and set a peak frequency value to a desired value by using a coarse equalization mechanism. The stage resistive load configured to provide tuneable equalization and low frequency fine equalization by using a fine equalization mechanism.

Abstract: Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.

Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Abstract: Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.

Abstract: A signal-to-noise and interference ratio (SNAIR) aware analog to digital converter (ADC)-based receiver and a method thereof is disclosed. The SNAIR aware-ADC based receiver comprises an analog front end (AFE) configured for recovering an input data signal with a bit error rate (BER) below a target BER. The SNAIR aware-ADC based receiver further comprises a sampler communicatively coupled to the AFE. A DSP unit is communicatively coupled to the SADC array. The DSP unit comprises a feed forward equalizer (FFE) configured to remove residual inter-symbol interference (ISI) by multiplying a delayed version of the digital data signal with Htap values. The CDR system is configured to process the generated plurality of error signals and data signals. An eye quality measurement system is communicatively coupled to an output of the DSP unit. A digital control communicatively coupled to each of the AFE, the sampler, the SADC array, the DSP unit, and the eye quality measurement system.

Abstract: Dual mode T-switches driven by at least one low-impedance switch driver, to connect at least four wires of a multiwire bus to a multi-input comparator (MIC) of a plurality of MICs in a first mode of Orthogonal Vector Signaling operation, and in a full-duplex mode of operation, using the low-impedance switch driver to disable a corresponding subset of T-switches to selectively disconnect a pair of wires of the multiwire bus from the MIC while using low-impedance enable signal paths in the low-impedance switch drivers to shunt capacitively-coupled interfering outbound signals received at the MIC from the selectively disconnected pair of wires in the full-duplex mode of operation.

Abstract: Methods and systems are described for selectively providing a signal path from a respective wire of a multi-wire bus to at least one corresponding data signal output node of at least one set of differential data signal output nodes using a respective switching element in a respective set of signal path circuits connected in parallel, and generating a set of discharge currents, each discharge current of the set of discharge currents generated through a respective resistive element in the respective set of signal path circuits to discharge a portion of a voltage pulse on the respective wire of the multi-wire bus to one or more metallic planes via a respective localized ESD protection circuit, the respective resistive element and the respective localized ESD protection circuit connected between the respective wire and the respective switching element.

Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Abstract: Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry, comprising a pair of latch input transistors which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry; and gain-stage circuitry, comprising a pair of cross-coupled gain-stage output transistors connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.

Abstract: Methods and systems are described for selectively providing a signal path from a respective wire of a multi-wire bus to at least one corresponding data signal output node of at least one set of differential data signal output nodes using a respective switching element in a respective set of signal path circuits connected in parallel, and generating a set of discharge currents, each discharge current of the set of discharge currents generated through a respective resistive element in the respective set of signal path circuits to discharge a portion of a voltage pulse on the respective wire of the multi-wire bus to one or more metallic planes via a respective localized ESD protection circuit, the respective resistive element and the respective localized ESD protection circuit connected between the respective wire and the respective switching element.

Abstract: Controllable voltage-signal generation circuitry, including: a plurality of segment nodes connected together in series, each adjacent pair of segment nodes connected together via a corresponding coupling capacitor, an end one of the segment nodes serving as an output node; for each of the segment nodes, at least one segment capacitor having a first terminal connected to that segment node and a second terminal connected to a corresponding switch; and switch control circuitry, wherein: each switch is operable to connect the second terminal to one reference voltage source and then instead to another reference voltage source, to apply a voltage change at the second terminal; the reference voltage sources and switches configured such that for each segment node the same voltage change in magnitude is applied by each switch, and such that the voltage change is different in magnitude from the voltage change applied by each switch of another segment node.

Abstract: Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry, comprising a pair of latch input transistors which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry; and gain-stage circuitry, comprising a pair of cross-coupled gain-stage output transistors connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.

Abstract: Controllable voltage-signal generation circuitry, including: a plurality of segment nodes connected together in series, each adjacent pair of segment nodes connected together via a corresponding coupling capacitor, an end one of the segment nodes serving as an output node; for each of the segment nodes, at least one segment capacitor having a first terminal connected to that segment node and a second terminal connected to a corresponding switch; and switch control circuitry, wherein: each switch is operable to connect the second terminal to one reference voltage source and then instead to another reference voltage source, to apply a voltage change at the second terminal; the reference voltage sources and switches configured such that for each segment node the same voltage change in magnitude is applied by each switch, and such that the voltage change is different in magnitude from the voltage change applied by each switch of another segment node.

Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.