Abstract: A flash memory device is provided, which may perform a read operation by itself without receipt of any command and/or address. The flash memory device may be used as a boot-up memory in a system. Additionally, it may be operable to also carry out normal write/read operations that may require command, address and control data from sources external the flash memory. During a system power-up, as the supply voltage increases, the flash memory device detects whether it is to be used as a boot-up memory in a system. The flash memory may then enter suitable operation modes in accordance with the detected results.

Abstract: A flash memory device is provided, which may perform a read operation by itself without receipt of any command and/or address. The flash memory device may be used as a boot-up memory in a system. Additionally, it may be operable to also carry out normal write/read operations that may require command, address and control data from sources external the flash memory. During a system power-up, as the supply voltage increases, the flash memory device detects whether it is to be used as a boot-up memory in a system. The flash memory may then enter suitable operation modes in accordance with the detected results.

Abstract: A semiconductor memory device includes page buffers having load transistors, each of which supplies load current to bitlines. The device also has a load control circuit, which is commonly connected to gates of the load transistor, having two discharge paths. The load control circuit discharges the gate voltage via the first discharge path when a gate voltage applied to the gates in read operation is higher than a target voltage, and discharges the gate voltage via the second discharge path when the gate voltage arrives at the target voltage. Therefore, it is possible to quickly set the gate voltage to the target voltage.

Abstract: A memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first state, the configurable decoder circuit is operative, responsive to receipt of an address associated with a portion, e.g., a block, of the memory array, to select the portion while producing a first status signal. In the second state, the configurable decoder circuit is operative, responsive to receipt of an address associated with the portion of the memory array, to prevent selection of the portion while producing a second status signal. The first status signal may indicate, for example, that the portion is valid, while the second status signal may indicate that the portion is invalid.

Abstract: A power on reset includes a latch controller and a latch circuit. The latch controller sets the latch circuit to an initialization state when a power supply voltage is less than a first threshold voltage during power-up, so that a power on reset signal from the latch circuit has the power supply voltage, a logical high level (i.e., goes to a logically activated state). The latch controller resets the latch circuit when the power supply voltage becomes higher than a second threshold voltage which is higher than the first threshold voltage, so that the power on reset signal goes to the ground voltage Vss, a logical low level (i.e., goes to a logically inactivated state). According to such a circuit configuration, even though the power supply voltage oscillates around a voltage at a point in time when the power on reset signal transitions from the power supply voltage to the ground voltage, the power on reset signal continues to be maintained at a previous set state.

Abstract: The disclosed is a nonvolatile semiconductor memory device which is employed in a system as a boot-up data storage component. The device includes a detection circuit for detecting a current level of a power supply voltage and for generating a detection signal. The detection signal is applied to the row and column selecting circuits, thus initiating an address designating memory cells that stores boot-up data. The boot-up data is then output.

Abstract: A method for programming non-volatile semiconductor memory devices having NAND cell arrays is provided. In a program operation, a pass voltage is applied to unselected word lines, and then a voltage lower than the pass voltage is applied to only the word line which is adjacent to a selected word line and is placed between the selected word line and a reference selection circuit. According to this programming method, the memory device can be programmed without restriction of programming sequence.

Abstract: Integrated circuit memory devices include circuits that can perform erase operations on multiple blocks of data simultaneously using preferred addressing techniques. The memory device contains blocks of memory cells and local decoders that are responsive to predecoded block address signals and electrically coupled a respective one of the blocks. A block size modifying circuit is electrically coupled to the local decoders and is responsive to a block size data signal and a first block address signal. The modifying circuit enables the simultaneous erasure of multiple blocks of memory cells during an erase time interval by generating the predecoded block address signals to select multiple ones of the local decoders simultaneously.

Abstract: A data read-out circuit is provided for a nonvolatile semiconductor memory having at least one bit line and a plurality of memory transistors connected to the bit line, and including at least one data sense line. The data read-out circuit includes a precharge set circuit, a current supplying circuit and a sense amplifier. The precharge set circuit is connected between the bit line and the data sense line and is operative to set a voltage of the bit line to a preselected precharge voltage lower than a power supply voltage. The current supplying circuit supplies a precharge current to the data sense line such that the bit line is precharged to the precharge voltage. The current supplying circuit also supplies a sense current lower than the precharge current, such that variation of the precharge voltage based on data stored in a selected memory transistor connected to the bit line is amplified to the voltage variation on the data sense line.