Abstract: A fan fault detection device includes: a plurality of sub-modules; and a master module to configured to determine faults of a plurality of fans, wherein each of the plurality of sub-modules includes: a first input terminal for receiving a detection signal indicating whether a corresponding fan is defective; a second input terminal; an output terminal; a switching circuit connected between the output terminal and a first power source for supplying a voltage signal corresponding to a state signal and, the switching circuit configured to switch an output of the state signal through the output terminal according to the detection signal; and a first signal transmission circuit connected between the first input terminal and the switching circuit, the first signal transmission circuit configured to transmit the detection signal to the switching circuit according to a signal received by the second input terminal.

Abstract: A fan fault detection device includes: a plurality of sub-modules; and a master module to configured to determine faults of a plurality of fans, wherein each of the plurality of sub-modules includes: a first input terminal for receiving a detection signal indicating whether a corresponding fan is defective; a second input terminal; an output terminal; a switching circuit connected between the output terminal and a first power source for supplying a voltage signal corresponding to a state signal and, the switching circuit configured to switch an output of the state signal through the output terminal according to the detection signal; and a first signal transmission circuit connected between the first input terminal and the switching circuit, the first signal transmission circuit configured to transmit the detection signal to the switching circuit according to a signal received by the second input terminal.

Abstract: An energy storage system (ESS) protection system includes: a battery monitoring system (BMS) configured to transmit a protection signal when an internal state or an external state of a battery cell is abnormal; a power conversion system (PCS) connected to the BMS through a hard wire, and configured to receive the protection signal through the hard wire; and an energy management system (EMS) connected between the BMS and the PCS through a universal communication line, and configured to receive the protection signal from the BMS and transmit the protection signal to the PCS. The PCS may be configured to perform an ESS shutdown when the PCS receives the protection signal through the hard wire or the universal communication line.

Abstract: An energy storage system (ESS) protection system includes: a battery monitoring system (BMS) configured to transmit a protection signal when an internal state or an external state of a battery cell is abnormal; a power conversion system (PCS) connected to the BMS through a hard wire, and configured to receive the protection signal through the hard wire; and an energy management system (EMS) connected between the BMS and the PCS through a universal communication line, and configured to receive the protection signal from the BMS and transmit the protection signal to the PCS. The PCS may be configured to perform an ESS shutdown when the PCS receives the protection signal through the hard wire or the universal communication line.

Abstract: A fan fault detection device includes: a plurality of sub-modules; and a master module to configured to determine faults of a plurality of fans, wherein each of the plurality of sub-modules includes: a first input terminal for receiving a detection signal indicating whether a corresponding fan is defective; a second input terminal; an output terminal; a switching circuit connected between the output terminal and a first power source for supplying a voltage signal corresponding to a state signal and, the switching circuit configured to switch an output of the state signal through the output terminal according to the detection signal; and a first signal transmission circuit connected between the first input terminal and the switching circuit, the first signal transmission circuit configured to transmit the detection signal to the switching circuit according to a signal received by the second input terminal.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material.

Abstract: A gate driver and a method of driving the same are disclosed. In one aspect, the gate driver includes a switching device, a pulse generator configured to generate a pulse signal. The gate driver also includes a pulse transformer configured to generate a gate voltage based on the pulse signal and apply the gate voltage to the switching device. The pulse generator is further configured to control the switching device by modifying a frequency of the pulse signal.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A gate driver and a method of driving the same are disclosed. In one aspect, the gate driver includes a switching device, a pulse generator configured to generate a pulse signal. The gate driver also includes a pulse transformer configured to generate a gate voltage based on the pulse signal and apply the gate voltage to the switching device. The pulse generator is further configured to control the switching device by modifying a frequency of the pulse signal.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.