Abstract: An integrated circuit device comprises multiple cores each comprising one or more separate input and output interfaces, the multiple cores integrated within the integrated circuit device to function as a single computer system. Internal inter-chip connection links are disposed on the integrated circuit device for connecting one or more cores with at least one other core via the one or more separate input and output interfaces. One or more bidirectional access ports are communicatively connected in each path of the inter-chip connection links to enable a separate external access point to each of the one or more separate input and output interfaces of the cores, wherein each of the one or more bidirectional access ports is dynamically selectable as each of an external input interface of the integrated circuit device and an external output interface of the integrated circuit device.

Abstract: An integrated circuit device comprises multiple cores each comprising one or more separate input and output interfaces, the multiple cores integrated within the integrated circuit device to function as a single computer system. Internal inter-chip connection links are disposed on the integrated circuit device for connecting one or more cores with at least one other core via the one or more separate input and output interfaces. One or more bidirectional access ports are communicatively connected in each path of the inter-chip connection links to enable a separate external access point to each of the one or more separate input and output interfaces of the cores, wherein each of the one or more bidirectional access ports is dynamically selectable as each of an external input interface of the integrated circuit device and an external output interface of the integrated circuit device.

Abstract: A method, system, and apparatus for maintaining the contents of a self-refreshable memory device during periods of data processing system reset is provided. In one embodiment, a refresh controller receives an indication that the data processing system is being reset. If necessary, the refresh controller modifies the signal from a memory controller to the memory device such that the memory device is placed in a self-refresh mode. The refresh controller keeps the memory device in the self-refresh mode until the data processing system re-enables external refresh signals.

Abstract: A method and arrangement is provided to support both fast Programmed Input/Output (PIO) and third party Direct Memory Access (DMA) data transfers between a system memory and Integrated Drive Electronics (IDE) drives. A DMA controller attached to an ISA bus supplies address, read and write signals in third party DMA data transfers. An IDE controller provides control signals to support the DMA data transfers. The IDE controller additionally provides address and control signals to support the PIO data transfers at local bus speeds. A local bus-ISA bridge is incorporated to support the system memory that resides on the local bus. An arbitration circuit arbitrates access to the ISA bus, and allows the IDE controller to seize the ISA bus for fast PIO data transfer.

Abstract: A computer system having a peripheral bus and a digital signal processor (DSP) local bus interfacing to the peripheral bus via an extended bus interface circuit (EBIC). The DSP local bus is configured such that devices, which are typically two or more DSPs, electrically connected to the DSP local bus may transfer data to other devices connected to the DSP local bus regardless of data transfer activity of the peripheral bus. Moreover, as seen from the peripheral bus, the devices connected to the DSP local bus have the same arbitration level. However, as seen from the DSP local bus, each device connected to the DSP local bus has a unique arbitration level determined by the priority of the tasks executing on the respective devices, as determined by a DSP operating system.

Abstract: A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. Devices coupled to the buses are either PCI bus-compliant devices or are non-PCI bus-compliant devices. A power management device in the computer system is able to place the computer system into a low power suspend mode, a resume mode and an active mode. The bridge has a multi-tiered arbitration device for arbitrating among the PCI bus-compliant devices and the non-PCI bus-compliant devices for control of the computer system. The arbitration device is responsive to the power management device to controllably suspend arbitration when the power management device indicates that the suspend mode is being entered.

Abstract: A DSP manager acquires through software techniques configuration and related data for multimedia hardware devices from BIOS device drivers interposed to functionally insulate the resource manager from hardware device specific information. The DSP manager manages tasks executing on hardware devices in a multiple DSP environment. The DSP manager optimally assigns tasks, loads tasks, and removes tasks for a function without interrupting execution of tasks making up other functions.